| A low-power, low-phase-noise fractional-N frequency synthesizer with an on-chip LC VCO has been developed in a 0.5{dollar},u{dollar}m CMOS technology. The on-chip VCO has the phase noise of {dollar}-{dollar}110dBc/Hz at a 200KHz offset with a carrier frequency of 973MHz. The tuning range is as large as 14%. The 1/f noise dominant frequency range is below 80KHz. The VCO alone consumes 6.6mW at a supply voltage of 3.3V.; A fractional-N synthesizer, which uses a higher-order sigma-delta modulator to suppress the fractional spurs occurring at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with a frequency resolution of f{dollar}rmsb{lcub}ref{rcub}{dollar}/64. The measured close-in RMS noise is less than 2 degrees with a loop bandwidth of 20KHz. The RF output has the phase noise of {dollar}-{dollar}111dBc/Hz at an offset frequency of 200KHz. The reference spurs are {dollar}-{dollar}73.4dBc. Fractional spurs are not present. The prototype dissipates 43mW, including the VCO buffer power dissipation, from a 3.3V supply voltage. |
