Built-in self-test for interconnect faults via boundary scan

In this dissertation, we have developed built-in self-test (BIST) techniques to test boards and systems via boundary scan (BS), to enable manufacturing and field test.; If BS is used to test faults in multi-driver 3-state nets, then the application of a test pattern that enables multiple drivers driving opposite values on a given net must be avoided. The single-enable constraints (SECs) that allow at most one enabled driver for each 3-state net are used to design BIST test pattern generators (TPGs) so that only conflict-free test patterns are generated. These constraints can be easily implemented using one-hot counters (OHCs) to generate tests for control cells of drivers of 3-state BS nets. For testing interconnects between non-BS devices (i.e., clusters), since there exist logic and multiple levels of 3-state nets, a TPG design comprised of a hierarchy of OHCs is developed to satisfy SECs. We have proved that the imposition of SECs in TPG designs for BS and cluster interconnects does not result in any loss of fault coverage.; The notions of incompatibility and conditional-incompatibility are developed to describe the SECs and constraints to guarantee complete fault coverage. A new optimization problem is formulated to obtain optimal TPG designs that satisfy all the constraints. For cluster testing, a new set of TPG requirements are identified and used during the design of the BIST architecture, whose satisfaction has been proved to guarantee conflict-free testing and coverage of all detectable faults.; Since configuration of a system changes frequently and each board is designed for use in a wide variety of systems, in the proposed BIST methodology for testing backplane interconnects, BIST circuitry on each board supports an inactive mode and an active mode, where the test objectives to be achieved by the board's BIST circuitry are described in terms of the board's own edge pin connections. A test schedule that activates BIST on each board in the system in a single-enable fashion is developed to test backplane interconnects independently of system configuration. This methodology has been proved to guarantee conflict-free testing and complete coverage of faults in backplane interconnects.