| Minimizing power consumption of CMOS IC ships becomes an important issue for cost and reliability concerns, as well as portable electronic applications. Deep submicron low power device design and analysis with the use of more accurate simulation tool are desirable due to the increasingly complexity and cost of IC fabrication, characterization, and testing. The work for this dissertation project is aimed at developing a more accurate simulation tool for deep submicron device modeling, as well as utilizing this newly developed simulator for deep submicron low power device design and investigation.;In this dissertation, the advanced transport models, such as electron and hole quantum mechanical models for both inversion and accumulation layers, local field accumulation layer mobility models, and hydrodynamic transport models, have been developed and implemented in 2-D device simulation tool---UT-MiniMOS. The dissertation work has resulted in an integration of the HD simulator of a simple quantum mechanical (QM) model as well as a more physically-based three-subband QM model for both electron and hole inversion and accumulation layers. With these enhanced abilities of the QM and HD models, the simulator will then be used for deep submicron low power device study.;The practical problem of 0. 1 mum NMOS device design and optimization has been investigated in order to illustrate some special features in deep submicron device physics and device design. Then alternative devices structures, such as devices with different high-K gate dielectric as well as SOI devices, will be examined as a possible solution for achieving high performance under low supply voltage conditions as devices scale down to 0. 1 mum region. |
