UT-MiniMos: A hierarchical transport model based simulator for deep submicron silicon devices

The challenge of Ultra Large Scale Integration (ULSI) of integrated circuits reinforces the need for accurate and efficient simulations to speed development and reduce cost. The predictive power of conventional simulation based on the drift-diffusion (DD) model has diminished to a critically low level. An improved transport model must now replace, what has been the foundation of semiconductor device simulation, the DD model. The hydrodynamic (HD) transport model, that addresses non-local effects such as velocity overshoot and carrier heating, is an attractive candidate. The true viability of the HD models in replacing the DD model rests on their availability in well-accepted device simulators, physical accuracy and ease of solution.; This work is an attempt to hasten and facilitate this replacement. The focus of this dissertation is an effort towards implementing a hierarchy of promising HD transport model candidates in an established and well-accepted device simulator using robust and efficient discretization and solution methods. Thus, UT-MiniMOS 3.0, a 2-D two-carrier integrated simulator for deep submicron silicon devices, has been developed to include a hierarchy of transport models and to construct a programming environment for easy implementation and maintenance of the physical models and numerical techniques. The hierarchy of transport models includes the DD model, post-processing current contour HD model, parabolic HD model, Stratton's energy balance model, Chen's energy transport model, Lee's HD model, Stettler's HD model, Bordelon's non-parabolic HD (NPHD) model, lattice temperature model, and Monte Carlo (MC) model. Each of these HD models is cast into a generalized HD formulation with four controlling parameters. This generalized HD formulation allows a unified discretization for all HD models. The NPHD model has been shown to provide the best overall agreement to MC energy, velocity and concentration. HD simulation in UT-MiniMOS for a bias point consumes less than one minute of CPU time on a IBM RS/6000 model 590 workstation for low and moderately high gate and drain biases, and less than two minutes for extremely high gate and drain biases.; Together with validated field- and energy-dependent mobility and substrate current models for hot carrier phenomena as well as lattice temperature model for self-heating effects, the hierarchical HD models in UT-MiniMOS 3.0 offer a flexible compromise between physical accuracy and computational efficiency for a wide range of needs of the device engineer. For example, one can start with the efficient DD and field-dependent mobility models to predict drain current characteristics. Accurate substrate currents may be obtained efficiently by the DD model attached with the post-processing current contour HD model. By paying about twice the CPU time, more accurate distributions of carrier energy and generation rate within the device are readily predicted by self-consistent NPHD simulation. Moreover, lattice temperature model may be used to predict the heating of the crystal lattice. Finally the physically most descriptive transport model in UT-MiniMOS, the MC model, may be employed to validate the insights gained by HD solutions or to perform detailed analysis of carrier transport. In this way, the device designer's needs may be met by moving up the hierarchy of transport models in a computationally efficient manner. In short, the richness in transport models as well as the efficient CPU and memory storage performances make UT-MiniMOS 3.0 an useful integrated device design tool for silicon ULSI.