A Study Of ESD Protection Device Based On Deep Submicron CMOS Technology

With the development of the integrated circuits (ICs), the device based on the deep submicron (DSM) technology is more vulnerable to the electrostatic discharge (ESD) zapping, which results in the circuit reliability problem. The gate grounded negative channel metal oxide semiconductor (GGNMOS) is one of the most effective ESD protection devices due to its simple operation mechanism and the compatibility with the complementary metal-oxide semiconductor (CMOS) process. However there are still many issues about the ESD events in advanced CMOS technology need to be solved. It’s also one of the important research directions for improving the reliability level of the DSM ICs. This dissertation mainly discusses the characteristics of GGNMOS protection device based on the DSM technology. The main studies and conclusive results are as follows:1. The simulation methods of ESD protection device have been studied. Based on the high current characteristic of ESD device, the physical models used in the numerical simulation are discussed. The simulation and analyzing are performed using the ISE-TCAD software. And the simulation parameters are calibrated by the test data. On the premise of the fully understanding of the GGNMOS operation mechanism, the way of building the circuit level model is studied. With the extraction of the necessary model parameters, the circuit level model is built with the Verilog-A language, which can be realized on the Spectre platform.2. A study of the effects of key layout parameters of GGNMOS is carried out. The transmission line pulse (TLP) test is performed on the GGNMOS manufactured with SMIC0.18μm CMOS technology. And then the device simulation analysis is made to evaluate the influence of key layout parameters of GGNMOS with silicide-blocking on the ESD level. The turn-on non-uniformity of the finger width is the physical reason for the ineffectiveness of the increasing of width on the ESD level promotion. The discussion about the heat dissipation volume in the short channel length turns out that the channel length should be compromised between the power and heat dissipation. The optimal principle of drain contact to gate spacing (DCGS) of the GGNMOS using the silicide blocking is analyzed in the view of electric and heat distribution. Meanwhile, the weak dependence of the ESD level on the source contact to gate spacing (SCGS) is proved.3. The dependency of protection device with different substrate type on the spacing between source diffusion and the substrate contact diffusion (SB) on has been presented. Considering the conductivity modulation effect, a substrate resistance model adjustable with the SB spacing is proposed. The relationship between the parasitic substrate resistance value and SB spacing with different substrate type is modeled for using in the circuit simulation. Also, the accurate prediction of the effect of SB spacing on trigger characteristic of GGNMOS is carried out efficiently.4. In order to improve the robustness of multi-finger GGNMOS, the substrate trigger technique is researched. By using the dynamic substrate resistance technique, a modified self substrate triggered gate grounded NMOS (SSTGGNMOS) is proposed. The simulation of I-V and temperature characteristics is performed based on0.18μm salicide shallow trench isolation (STI) CMOS technology. The results show a good failure current level of9.7mA/μm and32%improvement of trigger voltage. Comparing with the transient breakdown voltage of gate oxide, the new structure has better robustness. Meanwhile the discharging ability of the protection device is improved by the low turn-on resistance of0.5Ω.