High-frequency characterization and modeling of on-chip interconnects and RF IC wire bonds

Continuous scaling of transistors combined with increased chip area results in the ratio of global wire delay to gate delay increasing at a super-linear rate. For sub-0.25 μm technology and multi-gigahertz clock frequencies, on-chip interconnects may exhibit transmission line behavior. Simple RC models have become inadequate for simulation of modern VLSI circuits; parasitic inductance of the wires can no longer be ignored. In addition, parasitic inductance and capacitance of IC packages impose limits on the performance of circuits at high frequencies.; In this work, 3-D geometry-based physical extraction is exploited in the modeling of on-chip and off-chip inductance and capacitance. Modeling of on-chip inductance is presented for chips with power/ground wires and grids that emulate those used in practical circuits. The models capture 3-D geometry and process technology effects. Analytical formulae suitable for circuit design as well as for screening of inductance effects in CAD tools are developed to estimate the on-chip wire inductance. S-parameter characterization of fabricated chips up to 10 GHz shows good agreement with simulation and analytical calculations. Consideration of substrate effects may result in reduction of wire inductance when the spacing between the signal and ground wires becomes large. Eddy currents in ground planes or dense grids in a chip can also significantly reduce wire inductance. Design insight and suitable guidelines for minimizing interconnect inductance are demonstrated. On-chip capacitance modeling capabilities including 3-D rendering of solid objects, surface meshing, electrical parameter extraction for arbitrarily shaped objects are presented, which provide a direct link between design parameters and electrical performance.; Bonding wires are extensively used in IC packaging and circuit design in RF applications. An approach to fast 3-D modeling of the geometry for bonding wires in RF circuits and packages is demonstrated. The geometry can readily be used to extract electrical parameters such as inductance and capacitance. An equivalent circuit is presented to model the frequency response of bonding wires. To verify simulation accuracy, test structures have been constructed and measured. Excellent agreement between modeled results and measured data is achieved for frequencies up to 10 GHz.