A Study Of Automatic Layout Design For Multi-Chip SiC Module With Low Parasitic Inductance

As one of the critical steps in the design of power module,floorplanning has great impact on its reliability.Today,layout design relies heavily on the manual completion,which is labor-and time-consuming.Electronic Design Automation(EDA)is a trend in the future of electronics,which is why researchers are gradually focusing on the automatic design of the power module layouts.As a next-generation power device,silicon carbide(SiC)chips have many excellent properties compared with silicon counterparts,so their development has attracted much attention in recent years.However,limited by the manufacturing technology,their current capacity is not strong,so that more chips need to be paralleled in power modules.At present,the researchers generally used the genetic algorithm(GA)to complete the layout design of power modules.However,the increase in the number of devices seriously increases the population of the GA.In this situation,the GA cannot obtain accurate results in an acceptable time,and thus cannot be really applied to practice.In order to overcome the problem of time and precision caused by the large population,this paper proposed an automatic layout design method for the multi-chip modules,based on the hybrid idea of the EA and GA,which is more accurate,faster and more efficient.Firstly,we analyzed the feasibility of the hybrid idea of the EA and GA.For the optimal problem of large population,the GA is easy to converge prematurely.In view of it,the EA with parallel operation,which has high precision,was used to select the high quality part of the whole population,and then the GA is used to get the final result in the high quality population.This approach could improve the quality of the genetic population and greatly reduce the quantity,so as to ensure the accuracy of the final result and shorten the computational time.Secondly,based on the above idea,after determining the DNA position representation for components,this paper clarified the specific program,and simplified the parasitic parameter evaluation model and the genetic operation.After tested by a simple half-bridge module,the best parameters of the program were determined,and its fitness standard deviation was reached 0 in 115 minutes.By ANSYS Q3 D and PSpice validation,the case by our proposed method had the fitness up to 228,higher than that of the case mentioned in a congener method,so that chips in this case was subjected to a lower overshoot voltage during shutdown.Finally,this method was generalized to the automatic layout design of multi-chip modules.Based on the idea of simplifying the chips on the same bridge to a whole device,this paper proposed determining the optimal placement determination of parallel-connected chips,and then determined the best arrangement of switches and diodes after generating the DNA in the outer loop.In addition,a new chip connection model was added to solve the problem of reducing the precision caused by simplification.With a 12-chip and 3-terminal half-bridge module for example,ANSYS Q3 D and PSpice software verified that the layout case,which was output by our proposed method in 292 minutes,has the fitness value of 54.The layout case was better than the commercial module layout case,thus having a lower overshoot voltage.