On-chip inductance in high speed integrated circuits

It has become well accepted that interconnect delay dominates gate delay in current deep submicrometer VLSI circuits. With the continuous scaling of technology and increased die area, this situation is becoming worse. In order to properly design complex circuits, more accurate interconnect models and signal propagation characterization are required. Initially, interconnect has been modeled as a single lumped capacitance in the analysis of the performance of on-chip interconnects. With the scaling of VLSI technologies, narrower and longer wires with significant resistance have become commonplace. Currently, RC models are used to analyze high resistance nets and capacitive models are used for less resistive interconnect. However, inductance is becoming more important with faster on-chip rise times and longer wire lengths. Wide wires are frequently encountered in clock distribution networks and in upper metal layers. These wires are low resistance wires that can exhibit significant inductive effects. Furthermore, performance requirements are pushing the introduction of new materials for low resistance interconnect. One important example of these low resistance conductors is copper interconnect which has less resistivity as compared to the traditionally used aluminum interconnect. Copper interconnect is already used in many commercial CMOS technologies.;Inductance is therefore becoming an integral element in VLSI design and analysis methodologies. On-chip inductance is the focus of this dissertation in terms of anticipating related effects in VLSI circuits as well as developing appropriate design and analysis tools and methodologies that consider inductance in integrated circuits. Analytical expressions supported by simulation are provided to evaluate the importance of including inductance. These expressions characterize the magnitude of the error exhibited in the signal waveform and propagation delay when neglecting inductance and an RC model is used to model the interconnect. The effects of neglecting inductance on current design methodologies such as repeater insertion are also characterized to determine the penalty incurred if inductance is neglected. Fast and accurate tools for analyzing transmission lines and RLC have been developed. An equivalent Elmore delay is introduced for application to optimization and design methodologies. A repeater insertion algorithm targeting copper-based interconnect RLC trees is also introduced and used to optimize the delay across several industrial trees based on the equivalent Elmore delay model. It is shown that by neglecting inductance a significant cost in terms of delay, area, and power is incurred. Many industrial and experimental results are also presented throughout the dissertation in support of the presented theory.