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Wire Bonding Technology And Reliability Study Of A SiP Package Consisting Of CPU And DDR Chips

Posted on:2014-04-16Degree:MasterType:Thesis
Country:ChinaCandidate:P F ZhangFull Text:PDF
GTID:2268330401459324Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Along with the miniaturization, multifunction, high performance, high reliability and low cost of electronic system, advanced electronic packaging technology has become one of the most important technology in semiconductor industry. As SiP technique possesses the advantages of small size, short development cycle and development flexibility, it is being widely applied to many areas. In recent years, because the ratio between the number of integrated circuit chip terminals (I/O) and chip area will continue to rise,3D SiP package develops rapidly, however, its technology and reliability face more critical challenges. Hence, study of the3D SiP packaging technology and reliability has an important significance for development of our nation’s electronic package technology.This project studies the packaging processes and the reliability of the stacked-chip SiP package of CPU and DDR chips based on the module design of DTV receiver subsystem. In order to meet the requirement of the minimized package and rapid signal transmission between chips, the BGA package suitable for minimization was selected as packaging type, the3D stacked-chip package of CPU and DDR chips was adopted as packaging structure, and wirebonding technology was used as interconnection technology. In this study, the packaging design has been performed, including the packaging structure design, the PCB design, and the wirebonding distribution design and wire geometry design. The main work has been focused on the optimization of wirebonding parameters and reliability analysis.In this project. finite element analysis method and ABAQUS softwere were used to simulate the wire geometry structure parameters under the equivalent stress during the molding. Through the analysis, parameter windows of wire geometric structure were optimized and the effect of wire geometric parameters on wirebonding reliability is analyzed. In addition, some suggestions on wirebonding process are made, which provide a reference for wire geometric structural design during the wirebonding process.Based on the packaging design, the simulation and optimizition of wire structural parameters, and wirebonding empirical process parameters, the thermal ultrasonic wirebonding process parameters such as temperature, time, pressure and power were optimized by use of orthogonal tests. In this project,8mil Au wire was used as the bonding wire. A series of orthogonal tests such as the ball formation, the pull test, the wire tail, and the ball bonding tests were performed. The effects of wire bonding parameter on the bonding qualities were analized. The optimized process parameter windows were determined. The causes and mechanisms affecting the wire bonding reliability were discussed. In various factors affecting the wirebonding quality, bonding power and bonding pressure have a significant influence on bonding qualities. Results show that the bonding areas could be damaged by too large bonding power and the wirebonding strength was reduced. Defective bonding could be caused by too small bonding power. The bonding ball deformation could be caused by too large bonding pressure and the bonding strength could be also reduced by too small bonding pressure. The results provide a significant reference for wirebonding process to the project of DTV subsystem SiP package.
Keywords/Search Tags:Wire bonding, Wire structure parameters, Stacked-chip package, Orthogonal test, Finite element analysis
PDF Full Text Request
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