| Algorithmic Digital-to-Analog Converters (DACs) can offer small and low-power alternatives to other types of DACs for various applications. Despite these main advantages, the traditional designs for these converters are not competitive in terms of linearity, especially at high speed. This work is a thorough study of quasi-passive algorithmic digital-to-analog converters. The existing architectures for these converters are investigated, and the sensitivities that limit their performance are highlighted. Following the review, new concepts in the cyclic DACs are presented. Proposed improvements to the cyclic DAC include the differential bipolar architecture, better sample-and-hold, and digital calibration. Differential bipolar design increases the linearity by one bit and removes the largest nonlinearity from the midrange point. The new digital calibration scheme reduces the effect of capacitor mismatch very efficiently. Subsequently, a stray insensitive quasi-passive pipelined DAC is introduced which greatly boosts the linearity of the converter at high speeds. The novel pipelined DAC architecture is then enhanced with some of the same upgrades applied to the cyclic DAC. Additionally, through the use of multiplexed capacitors in the last stage of the pipelined DAC, the conversion speed can be more than doubled. Experimental findings on the implemented test chips support analytical and simulation results, and prove that the new algorithmic DACs can deliver comparable or better performance at lower power consumption compared to the current-steering DACs. |
