A study of floating-point analog-to-digital converters

The rapidly proliferating use of digital signal processing has resulted in an steadily increasing demand for higher sampling rates and lower power dissipation in high-resolution analog-to-digital converters. Application areas for high-speed, high-resolution converters include wireless communications systems, instrumentation for high-energy physics experiments, radar, and test and measurement equipment.; In recent years, switched-capacitor pipelined architectures have emerged as an especially attractive approach to implementing Nyquist-rate medium to high-resolution A/D conversion at medium to high conversion rates with relatively modest power consumption. In addition, floating-point A/D converters (FADCs) have been shown to be a useful means of providing a large dynamic range in applications where large signals need not be encoded with a precision greater than that needed for small signals. Owing to the nonuniform nature of the quantization in a floating point converter, it appears possible to sacrifice a large peak signal-to-noise ratio (SNR) to obtain savings in power dissipation and area while achieving a large dynamic range. The objective of this work is to combine the techniques of pipelining and floating-point conversion to achieve a significant increase in dynamic range without stringent linearity requirements or the overhead of complex calibration circuitry.; Floating-point analog-to-digital converters have historically been used for the instrumentation of experiments in which the acquired signal is of a non-repeatable nature, such as those resulting from explosions, impacts, or earthquakes. Specifically, they have been used for large dynamic range data acquisition in high-energy physics instrumentation, such as electromagnetic calorimeters for detectors in colliding beam machines. Additionally, nonuniform converters may be attractive for wireless applications in which a low-amplitude signals must be acquired and processed with a SNR in the range of 40 dB to 70 dB.; The research described in this dissertation includes the design of a front-end variable gain amplifier in which the output is fed to a uniformly-quantized pipelined converter with digital error correction. A 15-bit switched-capacitor pipelined floating-point A/D converter (FADC) has been designed with a 5-bit exponent and a 10-bit mantissa. The exponent value is established by a 3stage pipelined variable gain amplifier, while the mantissa is determined with a 10-bit uniform pipelined A/D converter. An experimental prototype of the converter has been implemented in a 0.5-μm CMOS technology. It achieves a dynamic range of 15 bits at a conversion rate of 20 Msamples/sec with a total power dissipation of 380 mW and an active area of 4.3 x 3.2 mm2.