Font Size: a A A

New techniques for integrated monolithic wireless receivers

Posted on:2003-10-25Degree:Ph.DType:Dissertation
University:Texas A&M UniversityCandidate:Elmala, Mostafa Abdelhakam IbrahimFull Text:PDF
GTID:1468390011481304Subject:Engineering
Abstract/Summary:PDF Full Text Request
The current interest in the portable wireless communications devices is promoting research into new IC technologies, circuit configurations and transceiver architectures. While transistor technology scaling and improved circuit techniques will contribute evolutionary advances in this field, architectural innovations in the transceiver may lead to revolutionary improvements in performance and more on-chip integration. Full receiver integration requires the elimination of off-chip high-Q image rejection and IF filters.; In this dissertation, two receiver architectures are analyzed in order to improve their performances. The first architecture is an implementation of the IF sub-sampling receiver. The main disadvantage of this architecture is the noise-folding problem. This receiver specifications are determined for a second generation (2G) GSM system with a 246MHz IF frequency, −102dBm to −20dBm input dynamic range, 200KHz channel bandwidth and 270kbps bit rate. The modulation is GMSK with a BT = 0.3. In this work, an on-chip active LC band pass filter that is used to shape the noise generated by the variable gain amplifier from aliasing to the signal band is presented. The filter has a center frequency equals 246MHz, and a maximum Q of 35. The noise figure of the IF to base-band stage of the receiver equals only 12.8dB.; The second architecture is an implementation of a self-calibrated image-reject receiver. The calibration is performed for the phase and gain mismatches in Weaver and Hartley architectures, which degrade the image rejection ratio. The chip fabrication is done only for the self-calibrated Weaver architecture. The input RF signal is at 1.8GHz, while the first and second local oscillator signals are at 1.6GHz and 200MHz, respectively. The implementation includes LNA circuit, mixing circuits, calibration loops, and variable delay-gain circuit. The measured image rejection ratio was improved from 26dB without calibration to 59dB after applying on-line calibration, without the use of any off-chip filtering.
Keywords/Search Tags:Receiver, Circuit, Calibration
PDF Full Text Request
Related items