Wireless Rf Receiver In The Research And Design Of Analog Baseband Circuit

In recent several years the wireless communication develops in an unprecedented speed with the leading of the handset equipment. Wireless communication had developed from the original voice and message delivery to the data-application and video stream communication. While the communication system is demanded of higher data-rate, the chips in-use are required for higher integration, lower production cost and less power consumption. Furthermore it is required that different communication prototypes can be realized by using a single hardware, thus the production cost and power consumption can be reduced a lot.A dual-mode analog baseband with digital-assisted calibration for WCDMA/GSM receivers is studied in the first part. The different modes switching can be realized by configuring Gain Bandwidth of the Operational Amplifier and the cutoff frequency of the filter. The Successive Approximation Register algorithm is adopted here to calibrate the DC-offset and the cutoff frequency automatically, and guarantee every gain stage works on a low offset condition without any bandwidth sacrifice of the analog baseband. After calibration the output offset is within5mV and the IM2measured is less than-63dB at a large output amplitude. The digital-assisted frequency tuning scheme can remain the cutoff frequency constant with the variation of process, voltage and temperature. The analog baseband achieves the reconfigurable bandwidth from200kHz to2.1MHz with the gain variation of6dB to54dB in3dB per step. The chip has been manufactured in SIMC0.13um CMOS process and consumes10mA in GSM mode including an on-chip buffer with the power supply of1.5V. The whole chip occupies1.2mm2and has been integrated in the transceiver system.An ultra-wide band analog baseband for mm-wave receiver is studied in the second part. The circuits process the signal in current domain. A high current gain is achieved at low power consumption by utilizing a cross coupled structure and a novel frequency compensation technique with noise cancelling is adopted to improve the bandwidth and noise performance. The chip has been manufactured in TSMC65nm CMOS process and occupies0.3mm2with the power supply of1.5V. The design is now under testing.