Modeling and simulation of electrostatic discharge (ESD) in MOS devices and circuits

Electrostatic charge buildup and dissipation or discharge commonly occurs throughout nature. When it happens through a discrete semiconductor device or a semiconductor device in an integrated circuit, the incident is referred to as an electrostatic discharge event. ESD often results in the failure of semiconductor components, as well as the system containing these devices. The effects of Human Body Model (HBM) that is one of the ESD events on semiconductor devices will be focused on this dissertation.; Substrate current is a good indicator for the hot-carrier and electrostatic discharge (ESD) related reliability of MOSFET. Chapter two in this dissertation develops an improved and analytic model for such a current based on the length of and maximum electric field in the high-field region near the drain junction. The present model is compared against several existing substrate current models reported in the literature, and results from device simulation and measurements are also included in support of the model development.; Chapter three develops such a model taking into account the effects of device geometry, impact ionization, and conductivity modulation. Comparison of the present and existing models is given, and results obtained from device simulation are included in support of the model.; Chapter four presents a comprehensive computer-aided design tool for ESD applications. Specifically, we develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. Experimental data measured from the transmission line pulsing technique (TLP) and human body model (HBM) tester are included in support of the model.; Chapter five presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown voltage and heat dissipation. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of 1 KV has been suggested. Furthermore, a case study to implement and optimize the ESD protection structure based on an existing 0.13-mum CMOS technology has been presented and verified.; In Chapter six, a new type of supply clamp is studied for the purpose of reducing the parasitic capacitance in ESD protection structures. (Abstract shortened by UMI.)...