Power Optimized ADC-Based Serial Link Receiver

A common trend in digital communications has been the increasing use of digital signal processing. There has been a growing interest in incorporating CMOS analog-to-digital converters (ADCs) as the frontend of high-speed serializers/deserializers (SerDes) and electronic dispersion compensation (EDC) of optical links. While the speed and resolution are achievable in CMOS technologies, the challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs.;This research focuses on system and architecture optimization to design a low power ADC-based receiver for serial link application. The proposed serial I/O receiver contains a low-gain mixed-mode and analog frontend (AFE) to pre-shape the signal. The requirement of both high-speed ADC and digital processing is dramatically relaxed which can reduce the power and also maintain the benefits of digital receiver. This research also introduces a non-uniform ADC reference setting that can compensate for undesired nonlinearity of the frontend, mismatch between interleaving paths, and optimally locate the slicing levels to maximize the voltage margins for the received signal. Furthermore, a new adaptation strategy of I/O link equalizers and clock data recovery (CDR) is presented based on minimizing the bit error rates (BER) as the objective function to maximize the receiver voltage margin. This technique enables near-optimal BER performance and requires almost no additional hardware compared to traditional adaptation approach.;Proposed techniques are verified in a 10 Gb/s ADC-based receiver in a 65nm CMOS technology. The measurement results show power-performance improvements by incorporating and jointly-optimizing the low-gain pre-filtering in an AFE and variable reference voltages for the ADC comparators. The combined techniques reduce the resolution requirement and amount of digital signal processing leading to reduced power consumption. The receiver consumes 130mW (13pJ/bit) in 1.1V supply for a 29dB loss channel and 106mW (10.6pJ/bit) for a 23dB loss channel. The results demonstrate the possibility of an ADC-based receiver being a viable scalable solution for next generation serial I/O receivers.