Design Of Signal Processing Platform For Digital Broadband Receiver

Due to worse electromagnetic environments where modern electronic receiving devices often work, analog receiving systems with worse anti-jamming abilities and agility unable to adjust. After 1980's, in order to utilize fully the digital processing techniques with higher reliability, better anti-jamming ability and agility, analog receiving systems are digitized gradually. And at the beginning of 1990's, the software radio is proposed. However, it is a tradeoff project to develop digitized receivers because of the imitations of analog-to-digital converter(ADC), digital signal processing(DSP) etc. Therefore,it's significant to develop highly effective wideband digital receivers, which can be used to digitize the wideband communication receiving systems, improve the performance of the communication receiving systems such as Radar, Telemetry, etc, and implement the desired receiving systems based on software radio.Currently, the studies of Digital Receiver are mainly concentrated in the dynamic range, DDC technologies, real-time and efficient digital channelization, the technology of digital coherent demodulation, and so forth. With the higher performance of FPGA and the innovation from ADC chip, the comprehensive performance of digital receiver is achieving steady improvement, the capabilities of digital signal processing has notably improved. The thesis made single channel autotracking receiver as research background, and carried a profound studies and debates toward pretreatment technologies concerning DDC and digital channelization, the main contents of the thesis are as followings.In terms of the demand of single channel autotracking receiver of some band in a research institute, the author designed a digital receiver hardware implement scheme which meet the standards, and introduced different parts of the receiver. The digital receiver mainly composed of high-efficiency ADC chip named AD9680?the knock-out product FPGA of the XILINX and the powerful DSP chip. Sampling rate and the bandwidth of front-and processing reached 600 MHz and 300 MHz respectively. The bandwidth divides into 16 channels and these are under detection and demodulation simultaneously. AD and FPGA digitally communicate by utilizing high speed link technology JESD204 B, the communications between FPGA and the latter DSP are achieved by high speed serial Rapid IO, DSP mainly detect and track the 14 channels.Digital receiver of DDC functions is completed in AD9680 chip, and analyses the two typical methods of DDC implementation: low pass filtering method and the polyphase filter method, AD9680 take the first. By experimental analysis, simulation and board test, the DDC functions in AD9680 meet the design requirements, and moves the signal to the baseband, and takes two times extraction. JESD204 B transmission protocol and transmission scheme are presented, whose single channel transmission rate is reaching 6.0 Gbps.Digital channelization was implemented in FPGA, which was based on polyphase filtering structure, whose bandwidth is 300 MHz with each channel width of 18.75 MHz. Modular design was given on the implementation of digital channelized in FPGA, whose main modules included: extractor, symbolic transformation, channel filter, secondary mixing and FFT, and the FPGA resources were analyzed. Under the MATLAB simulation and board test, the result meted the requirement.Finally, high-speed serial Rapid IO was presented, and introduced the protocol composition and some key factors in real use, including the configuration of IP core, the relationship between the clock and link to send the design of the module. DSP signal processing flow was given briefly.