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Digital Pulse Ultra-wideband Receiver And Key Module Design

Posted on:2011-08-07Degree:DoctorType:Dissertation
Country:ChinaCandidate:K ShaoFull Text:PDF
GTID:1118360305997155Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The impulse radio ultra-wideband (IR-UWB) system uses narrow pulses to transmit information. It is very suitable for wireless security communications, short range high speed wireless data transmission, and precise localization applications due to its outstanding advantages such as low power consumption, low cost and high data rate. A deep research of digital structure IR-UWB receiver and the design of key modules of the receiver are presented in this thesis.In the research of digital structure IR-UWB receiver, the key points of design are analyzed and the sub-sampling technique is proposed to solve the power and design complexity problem of the ADC in this receiver. A relationship between sub-sampling technique and IR-UWB system is also discussed. After that, a frequency synthesizer is proposed to guarantee enough SNR of the sub-sampling receiver. The jitter performance of this synthesizer should be less than 1% of the sampling period.According to low power, low cost requirements of IR-UWB system and the primary specifications of each modules, a time-interleaved 4224 MS/s 1 bit Flash ADC and an integer-N LC PLL are designed as two key modules of the receiver. Good tradeoff between speed, accuracy and power consumption is achieved in ADC and PLL by using a lot of low power design techniques and performance optimization strategies. Measurement results indicate that at 4 GHz sampling rate, the ADC consumes 22.8 mW power and occupies 0.25 mm2 area when the frequency of input signal is 4.2-4.8 GHz; The PLL achieves RMS jitter of 0.57 ps and reference spur of-63.14 dBc at carrier frequency of 4224 MHz. The power consumption and the area of LC PLL are 18 mW and 0.81 mm2, respectively.To overcome the disadvantages of traditional time-interleaved Flash ADC and integer-N LC PLL, while still satisfy the requirements of the receiver, a new structure is proposed to significantly reducing power, cost and design complexity of these two modules. In the new structure, equivalent sampling and self-calibration technique are used in ADC to ensure less than 10 mV accuracy at 4224 MHz sampling rate, while consumes 2.4 mW power and occupies 0.81 mm2 area. Shifted-averaging and duty cycle correcting techniques, VCO noise optimization and spur suppression strategies are used in the ring oscillator based PLL to improve the its phase noise performance. A RMS jitter of 1.53 ps and reference spur of -66.81 dBc are achieved at carrier frequency of 264 MHz. The power consumption and area of this PLL are only 4.23 mW and 0.14 mm2, respectively. Moreover, no MIM capacitors or on-chip inductors are used in new ADC and PLL, the measurement results also indicate that these two chips can work correctly even below 1 V supply voltage.
Keywords/Search Tags:IR-UWB, digital receiver, sub-sampling, ADC, PLL, low power, CMOS, sample and quantize, ring oscillator
PDF Full Text Request
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