| The test schedule and associated hardware determine the quality, complexity, and efficiency in SoC (System-on-Chip) testing. According to Semiconductor Industry Association Roadmap, test scheduling is one of the big challenges anticipated in future SoC testing. TAM (Test Access Mechanism) and power consumption are two main constraints in test scheduling. In general, there are three methods to develop the test scheduling. They are: (1) graph based method, (2) bin packing method, and (3) ILP/MILP (integer linear programming/mixed integer linear programming) method. So far, the graph based method can only deal with basic TAM features and simple (e.g. one peak or average value) power constraints. The bin packing method covers more comprehensive TAM features and simple power constraints. The MILP method, published so far, can only solve fixed TAM with a few optional features and simple power constraints.; In this dissertation, we first propose a test interface circuit (TIC) and an ILP formulation to allow testing high-speed circuits with low-speed ATEs (Automatic Test Equipments) without considering power. The TIC's role is to match low frequency of ATE with high frequency of circuit under test (CUT) by storing part of test data in its memory and delivering them at the right time. Our ILP formulation optimizes the test transfer time and the interface memory cost with an actual test data transfer schedule. This flexible environment explores the options, performs tradeoff between time and cost and achieves true (or very close to) at-speed test of CUT without changing the electronic characteristics of the CUT.; Later, two MILP formulations, MILP-C and MILP-A, are presented that perform power-time tradeoff by considering power of non-embedded cores and selected areas, respectively. They both take information about power consumption of non-embedded cores (i.e. power profile) into account. This includes power profile over time as test patterns are applied for MILP-C and over area units, called grids (i.e. power distribution across physical area of layout) for MILP-A. Our method optimizes the test schedule to achieve minimum overall test time or minimum power consumption. MILP-C considers the peak and/or average power consumption of cores, time/sequencing requirements and the optional ATE pin limitation as constraints. In MILP-A, the total peak power of grids associated with cores inside the selected areas, is used to avoid the formation of hot-spots during test. (Abstract shortened by UMI.)... |
