| The pipelined analog-to-digital converter (ADC) is widely used in high-speed, high-resolution analog-to-digital conversion applications. The advantages of using the pipelined architecture include low power and small area. One drawback of the pipelined architecture is that when used for high-resolution applications, the first few stages of the pipeline require high linearity and low noise. With scaling of CMOS technologies, high-precision analog building blocks become more difficult to design, while the cost of digital circuits shrinks in terms of both area and power. One approach to designing a pipelined ADC in modern CMOS technologies is to shift design complexity from the analog domain to the digital domain. In particular, a pipelined ADC can be designed with low-precision analog building blocks and the resulting non-idealities can be corrected digitally.;To demonstrate the feasibility of shifting design complexity from the analog domain to the digital domain, a 12-bit 40 MS/s pipelined ADC prototype is implemented with a few different low-precision analog building blocks and the resulting non-idealities are all corrected digitally. To begin, an integrator-based residue amplifier is implemented in the first stage of the pipeline. In addition, outputs of the traditional residue amplifiers used in later stages are sampled before settling. Finally, to reduce coupling between stages through shared reference voltages, three separate reference voltage generators are used in the pipeline. The nonlinearities arising from the integrator-based residue amplifier, from the early sampling of the residue-amplifier output and from the separate reference generators are all corrected digitally. Overall, calibration improves SFDR from 50.8 dB to 92.4 dB and improves SNDR from 42.7 dB to 68.8 dB. The prototype ADC's power dissipation is 140 mW. |
