Effects of gate tunneling currents on the static characteristics of CMOS circuits

The continuous scaling of transistor dimensions over the past thirty years has required the use of thinner gate oxides in MOS devices. It is projected in the ITRS [1] that gate oxide thicknesses in the 1.6 nm to 0.6 nm range will be used in future generations of MOS integrated circuits. Gate tunneling currents increase substantially in such thin oxides. The effects of gate tunneling currents in thin oxide CMOS circuits are studied. Trends in performance characteristics such as noise margin, signal swing, and static power consumption in the near term ITRS technology generations are obtained. It is found that static performance characteristics degrade with scaling and show a dependence on fanout in static logic circuits. One of the most important properties of CMOS logic circuits, their low standby power consumption, is severely affected by the presence of gate tunneling currents. The tunneling currents in MOSFETs connected to form a stack are different depending on their position in the stack. The dependence of static power consumption in CMOS logic gates on input vectors is studied. A voltage-controlled current source (VCCS) model for gate and drain currents in MOSFETs is developed. The VCCS model can be used for sizing transistors in a stack so that the output voltage degradation is minimized. This model can also be used to perform hand calculations of signal swing degradation and static power consumption when the logic circuit is in a static state. The impact of gate tunneling currents on read/write access delays and static power in SRAMs is obtained. An alternative all-PMOS circuit for the SRAM cell is proposed that reduces the static power consumption in the SRAM cell by nearly an order of magnitude in comparison with a conventional SRAM cell.