Study And Optimization Of Gate-all-around TFET DC/AC Characteristics And Evaluation Of Its Benchmark Circuits

As integrated circuits developed to the 5-nanometer technology node,the continuous growing demonds of market for both power and speed are difficult to be met by the simply reduction of device physical size.Therefore,many researchers have proposed a number of novel low-power devices.Tunneling field effect transistors(TFETs)benefit from the band-to-band tunneling(BTBT)mechanism,leading to the sub-threshold swing(SS)break-through of the 60m V/Dec of traditional MOSFETs.Then,TFET stands out among many low-power devices and becomes a promising candidate in the next-generation ultra-low-voltage integrated circuits.However,TFET also suffers from some crucial drawbacks such as low ON-state current,large Miller capacitance,and ambipolar current,which makes it hard to be in application.This paper combines the gate-all-around(GAA)structure with TFET band-band tunneling,and by joint modeling,the design of the GAA-TFET device and its benchmark circuits are optimized.Moreover,the device structure parameters and circuit power-speed trade-offs are analyzed.The main research content and results are as follows.(1)The device-circuit co-optimization platform are established.Based on the calibrated physical models,the I_ds-V_gs,C_gs-V_gs and C_gd-V_gs curves under diferent V_dsare obtained by TCAD simulation,and the data is transferred into two-dimensional lookup tables.Based on the lookup table,the Verilog-A behavioral model for GAA-TFET device under several structural parameters are established.The transfer characteristic curve obtained by the model is compared with the curve simulated in TCAD,and the maximum deviation is within 0.50%,which assures the accuracy of the circuit simulation adapting this model.(2)Based on the Sentaurus TCAD simulation of the GAA-TFET device,the impacts of structural parameters on its electrical characteristics are analyzed.The results show that when the gate-drain underlap length(L_UN)is 10nm,the ambipolar current of the device can be reduced by an order of magnitude,while the gate-drain capacitance is reduced by 37.93%.When the gate-source overlap length(L_OV)is 10nm,the tunneling distance of the device tunnel junction can be reduced to 50%of that of the non-overlapped device,thereby the ON-state characteristics are improved.As for the asymmetric asymmetric dual-layer gate oxide structure,the device with the best performance is when L_OXS is 5 nm.Compared with symmetric structure,there is 34.30%increase in on-current,and compared with 30-nm L_OXS structure,there is 18.32%reduction of bipolar current and 19.37%reduction of gate-drain capacitance.In addition,the influence of asymmetric gate metal work function and pocket region in the channel on the transfer and capacitance characteristics of the device is also explored.3)Through joint modeling,the influence of the structural parameters of each device on the power-delay trade-offs of the inverter under different supply voltages(V_DD),the static noise margin(SNM)and read/write delay of the SRAM circuit are analyzed.The results show that when the device L_UN=10nm,the propagation delay of the inverter is reduced by 44%compared with the inverter built with no gate-drain underlap device,and the energy consumed per cycle is reduced by 36%,and its minimum energy-delay production is when V_DD=0.5V.As for the asymmetric gate oxide structure,the inverter built with 10-nm L_OXS device has the smallest propagation delay.The propagation delay is reduced by 27.48%when the pocket length(L_po)in the channel region is 10nm,compared to that built with the device without the pocket region,and when the pocket region doping concentration is 10¹⁹ cm^-3,the propagation delay of the inverter is reduced by 45.86%compared with that built with 10¹⁵cm^-3 doped pocket region.In summary,the research results of this paper can provide an important reference for the optimization of GAA-TFET structural parameters and its circuit applications from the perspective of power-speed trade-offs.