Design Of CMOS Logic Circuits Based On Nanodevices

Using non- equilibrium Green’s function and Poisson equation, calculation model of carbon nanotube Field- Effect Transistor(CNTFET) is built. In order to explore the electrical properties of the two novel nano device structures, self- consistent calculation of CNTFET is performed. Using the HSPICE with look- up table based Verilog- A models, the performance parameters of circuit have been calculated. Furthermore, due to the shrink of device dimensions, the impact of gate leakage current tunneling effect caused by the reduction of oxide layer thickness to the functionality of circuits is investigated. The main works of this paper are as follows:Firstly, a new CNTFET with Single Halo doping(SH- CNTFET) has been proposed. Compared to the Conventional CNTFET(C- CNTFET), the impact of single Halo implantation on the performance of CNTFET has been explored and it is revealed that SH- CNTFET has an improved RF and switching characteristics. At circuit level, results show that, compared to a C- CNTFET based inverter, the SH- CNTFET based inverter exhibits a better performance. It is shown that SH-CNTFET Static Random Access Memory(SRAM) has an improved performance in Static Noise Margin(SNM), Power Delay Product(PDP) and write power compared to C- CNTFET SRAM and the optimum Halo doping level has been concluded.Secondly, a new CNTFET of Light doping Hetero gate dielectric Tunnel Field- Effect Transistor(LD- HTFET) has been proposed. Compared to the High K gate dielectric TFET(HK-TFET) and Hetero gate dielectric TFET(HTFET), it is revealed that LD- HTFET has a better static and high- frequency properties. On the one hand, heterogeneous dielectric helps in reducing the gate capacitance and improving high- frequency properties. On the other hand, light doping can effectively improve on/off current ratio. Furthermore, performance of inverters using p- i- n FETs has been investigated for different supply voltage. The results indicate that, LD- HTFET based inverter shows a better performance in terms of power, SNM and gain.Thirdly, the formation mechanism of gate current is studied and the device models of gate current is established. Based on the two- input AND gate, due to the shrink of device dimensions, the impact of gate leakage current caused by the reduction of oxide layer thickness to the functionality of circuits is investigated. It is shown that when the oxide layer thickness is 0.5nm, due to the impact of the gate tunneling effect, it makes the circuit logic error.