Gate tunneling in MOSFETs and dynamic characteristics of MOS integrated circuits

Aggressive scaling of MOSFETs projects devices with oxide thicknesses as small as 6 A in the near-term. At these dimensions, electrons can easily tunnel through the gate oxide barrier. The impact of large tunneling currents on the properties of MOSFETs is not well known. Quantum tunneling through MOS barrier structures has been studied in isolation from a quantum physics perspective, but has not been integrated into a device context. Furthermore, the impact of large tunneling currents on the performance of CMOS logic circuits is also not well known. Classical MOSFET compact models do not incorporate gate tunneling currents. Attempts to include gate tunneling currents in compact models and circuit simulation resort to either macromodel wrappers around classical compact models, or inconsistent and unphysical techniques. In this thesis, the impact of gate tunneling currents on the operation of the MOSFET is studied in detail and a new model for the NMOSFET in strong inversion with gate tunneling current is derived. MOS devices with gate tunneling are simulated in MEDICI and a simple model for gate tunneling currents in a device context is proposed. The system of equations for the operation of a MOSFET is then revisited with the presence of gate tunneling current and an approximate strong inversion model is derived. Furthermore, the impact of tunneling on dynamic performance of CMOS circuits is assessed. A broad range of simulations are performed in HSPICE to isolate the impact gate tunneling will have on circuit operation. New models for power dissipation and dynamic noise margins are derived that account for the presence of gate tunneling currents and are shown to correlate well with simulation results.