Power-thermal modeling and management of integrated circuits and systems

Power has become one of the primary design constraints for modern processor designs. In this dissertation, we first study optimal voltage scaling for best performance with dynamic power and thermal management under different packaging options. Considering concurrent repeater and Flip-Flop (FF) insertion, we also study microarchitecture-level interconnect prediction for power and performance. After that, we evaluate the potential of microarchitecture-level leakage reduction and study microarchitecture-level leakage energy reduction by power gating. We show that the ideal leakage energy reduction can be up to 30% of the total energy for the modern high-performance VLIW processors we study. We further improve the existing adaptive cache decay method for leakage reduction with data retention. Furthermore, we study temperature and supply voltage aware performance and power modeling at the microarchitecture level. We present a leakage power model with temperature and voltage scaling, and demonstrate the necessity of temperature-aware power modeling in dynamic power and thermal management.;Beyond the scope of traditional monolithic uniprocessor architecture, Chip Multi-Processing (CMP) architecture has become increasingly attractive for better system performance. In this dissertation we study power-optimal Voltage Scaling and Voltage domain Partitioning (VSVP) problem for CMP architecture, subject to constraints on performance and the area overhead of on-chip dc-dc converters. To efficiently explore the large multi-dimensional solution space, we develop an analytical performance model for CMP considering on-chip communication contentions and heterogeneous Vdd for processor cores. Considering a CMP with voltage scaling capability and Quality-of-Service (QoS) guarantee, we show that with the consideration of on-chip dc-dc converters, the optimal voltage domain number may not be the maximum domain number available. Such result clearly shows that the assumption in existing low power task and voltage scheduling methods for multi-processor systems that a system always contains maximum number of possible voltage domains (one processor core per domain) may not lead to optimal power for CMP with on-chip dc-dc converters. Furthermore, we apply our analytical performance model to study the performance-optimal CMP design and scaling issues. We show that technology scaling has a diminishing or saturated throughput increase for single-core design, but multi-core design with a same area improves throughput by 5.58X when scaling the technology from 65nm to 32nm.