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Research On Key Technology Of Power Efficiency Designs Of Network-on-Chip With Voltage/Frequency Islands

Posted on:2013-09-06Degree:MasterType:Thesis
Country:ChinaCandidate:B LiuFull Text:PDF
GTID:2248330395980554Subject:Military communications science
Abstract/Summary:PDF Full Text Request
With the rapid development of Network on Chip (NoC), energy consumption has becomean increasingly important problem. Power Efficiency Designs of NoC with voltage/frequencyislands have drew extensive attention for substantially reduced energy consumption.At present,there are still many problems in key techniques o f existing designs, witch can be outlined as:1.Whether dividing voltage/frequency island before or after Intellectual Property Core (IP Core)mapping, the existing voltage/frequency island partitioning methods have difficult to furtherreduce the total energy consumption.2. The existing energy aware routing algorithm withvoltage/frequency islands didn’t use communication energy consumption model, which causehigher communication energy consumption and lots of communication hot spots is anotherquestion in them.3. The existing Dynamic Voltage and Frequency Scaling (DVFS) controlalgorithms have poor system stability.To slove the questions in voltage/frequency islands partitioning, this dissertation presents avoltage/frequency island partitioning method based on genetic algorithms. In order to furtherreduce communication energy consumption, this dissertation presents energy aware routingalgorithm with voltage/frequency islands. Then, a DVFS control algorithm based oncharacteristics of the inter-island queues is proposed to futher reduce total energy consumption.The contributions of this dissertation are outlined as follows:1. A voltage/frequency island partitioning method based on genetic algorithms is proposedto solve the problems in voltage/frequency island partitioning. By using genetic algorithm codingmethod, this method combine voltage/frequency island partitioning with IP core mapping, andfinishes those two design steps at the same time. In order to meet the deadline constraints, thismethod uses penalty function to ensure the algorithm to operation correctly and convergencequickly.Simulation results shows that, this method takes a long run time, but reduces the totalenergy consumption effectively.2. An energy aware routing algorithm with voltage/frequency islands is proposed. Usinggenetic algorithm and take communication energy consumption as the objective function, thisalgorithm gets a low power consumption. To solve the problem of communication hot spots inexisting routing algorithms, this algorithm use penalty function to reduce communication hotspots on the premise of satisfying the communication delay. Simulation results shows that,compared with the existing algorithms, this algorithm cost small amounts of resources on chip,the algorithm gets optimization of two aspects—communication energy consumption andcommunication hot spots.3. A novel DVFS control algorithm based on characteristics of inter-island queues isproposed. This algorithm uses utilization rate and growth rate of inter-island queues for DVFScontrol. This algorithm use growth rate of inter-island queues to forecast work load, improvedthe efficiency of the algorithm. After comprehensively considered the demand of the input/outputqueue on island’ voltage and frequency, this algorithm improves the stability of thesystem.Simulation results shows that, compared with existing algorithms, this algorithm reduces only little energy consumption,but optimizes the stability of the system obviously and improvesconsumption performance.
Keywords/Search Tags:Network on Chip, Voltage/Frequency Island, Energy effict, Routing algorithm, IPcore mapping, Dynamic Voltage and Frequency Scaling, Genetic Algorithms
PDF Full Text Request
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