Low Voltage and Low Power Circuit Techniques for CMOS RF Frequency Synthesizer Application

Over the past decades, wireless communication has experienced a remarkable development and become an essential part of daily life. With the rapid increasing demand for mobile and portable electronic devices, the power dissipation has become one of the most critical design parameters, especially for RF front-ends. In portable wireless consumer electronics, the RF frequency synthesizer is one of the most power-consuming subsystems, which serves as local oscillator (LO) in transceiver design. Any power saving in frequency synthesizer will directly affect the running time of battery.;To demonstrate recent innovation in low power techniques, three different circuit blocks and one frequency synthesizer have been developed and fabricated in low-cost 0.18-microm triple-well CMOS process. The first design is a low-voltage current reused quadrature VCO and divider-by-4 frequency divider circuit. By the novel sharing of transistors between the two high frequency blocks, the power consumption of the overall design can be reduced with little penalty on voltage headroom. Experimental results show a phase noise level of -114 dBc/Hz at 1 MHz offset from 2.2 GHz carrier and consumes 2.7 mA from a 1.3V power supply. The second design is a transformer-based current reused VCO/ILFD circuits for SDR application. By the adoption of bias tuning techniques, variable division ratios (2,3,...,9) can be achieved with a single divider circuit. Experimental results show an output frequency ranging from 0.58 to 3.11 GHz and a phase noise level of -112.5 dBc/Hz at 1 MHz offset from 5.72 GHz carrier, with a consumed current of 4.7 mA from a 1.8V power supply. The third design is a transformer-based current-reused QVCO/SSBM circuit for UWB application. The prototype is the first of its kind, while occupies a core area of 0.8 mm2 and consumes roughly 11 mA from 1.6V power supply. Measurement results show that the out-of-band spurious rejection and phase noise at 1 MHz offset are better than 43 dBc and -112 dBc/Hz respectively. The final design is a frequency synthesizer for MB-OFDM UWB application. It uses a single inductor approach and novel system architecture to realize compact die size and low power consumption without sacrificing major performance. Experimental results show a phase noise level of -119 dBc/Hz 10 MHz offset for all UWB bands and consumes 24.7 mA from a 1.2 V power supply.