Design of low power, low phase noise, high resolution RF CMOS frequency synthesizer

Phase locked loop based frequency synthesizer is one of the major building blocks in radio frequency (RF) integrated transceivers where frequency synthesis of local oscillator is usually done using a gigahertz-range PLL. The phenomenal growth in modern telecommunication systems has developed increasing demand for high-speed synthesizers with low phase noise. Designing high-speed and low-noise CMOS synthesizers is desirable, however, presents challenges for its stringent design requirements. The design constraints are low timing jitter, low phase noise, low spur and high resolution. This thesis examines various circuit techniques to overcome fundamental limitations in designing high-speed, low-power, low-noise and high-resolution synthesizers. Different topologies of synthesizers are proposed for various system applications with different system specifications.; Some synthesizers are used in RF transceiver where a number of closely spaced RF local oscillator frequencies need to be created to select the desired incoming channel. This thesis presents a low-noise and low-power synthesizer with variable speed capabilities for ZigBee system applications. A new, low-power and low-noise prescaler and programmable multimodulus frequency divider are designed, fabricated, tested. A fully differential LC-based VCO and a new charge pump with good matching properties have been implemented for this synthesizer. Simulation and experimental results are presented that validate the circuit.; With the advent of wireless personal area network (WPAN), there is a need for low-cost synthesizer whose phase noise requirement is less stringent than that required in more conventional standards such as GSM. This thesis describes a low power synthesizer using wideband, on-chip ring VCO for 'Zero-G' system, where low-cost is the major concern.; The self-calibration technique helps in designing wide band synthesizers with low noise operation. A methodology is described to design a high-speed, low-jitter auto-calibration synthesizer that calibrates against mismatches in the components and process variations and also provides a possible Built-in-Self-Test (BIST) solution for the synthesizer embedded in a chip. The severe tradeoff between the channel frequency spacing and frequency switching time of Integer-N synthesizer is alleviated by using fractional-N synthesizer. This thesis presents a new 4th order digital Deltasum modulator that is used for fractional division ratio generation for the application of high-resolution fractional-N synthesizer.