Loop Modeling Of C-Band Frequency Synthesizer And Circuit Design Of Low Phase Noise VCO

A ?-? fractional-N frequency synthesizer is designed for 5G communication system.According to the radio system agreements,the frequency range of the synthesizer covers from 1 GHz to 8GHz by two separate VCOs based on the structure of charge pump in PLL.Based on the research background and application,the principle and specification of the frequency synthesizer are introduced to determine the structure.Then the linearization model and the phase noise model of the charge pump PLL are analyzed to model the charge pump PLL.According to the linearization model of the PLL,loop parameters are also calculated and optimized by the Verilog-A model of the PLL.Finally,a VCO is designed and the test results are given.The frequency synthesizer is designed by 0.18mm SiGe BiCMOS technology.The test results show that the frequency of two VCOs covers the range from 3.88 GHz to 7.75 GHz,at 6GHz with the phase noise-114.7616 d Bc/Hz@1MHz and-87 d Bc/Hz@10k Hz respectively.Since the output of VCO can be divided by 2 or 4,the output frequency of the synthesizer can cover 1GHz-7.75 GHz,which fully meets the sub-6G band of 5G standards.