Building high speed, energy-efficient CMOS circuits using variations in circuits techniques

Complementary Metal Oxide Semiconductor (CMOS) circuit technology has become the cornerstone of microprocessor design. It has replaced TTL (Transistor Transistor Logic) and ECL (Emitter Coupled Logic) in nearly all application domains. However, for high speed systems, CMOS gates have serious speed limitations not found in the other technologies. These problems have lead to a growth of research in high speed CMOS gate design. Concurrently, in the past four years there has been an enormous growth in the portable computer market. All indicators predict that this trend will continue. As a result, low-power/low-energy design has become an important issue at all levels of microprocessor design. This work investigates energy consumption at the circuit level. One goal of this thesis is to empirically demonstrate that by broadening the design alternatives to include unconventional logic families, circuit speeds can be significantly increased in an energy efficient manner.;Low-power design is not only important for microprocessors but also for the next generation of multimedia-based personal digital assistants, or PDAs. Unlike a microprocessor, most of the logic inside a PDA will be devoted to image compression and decompression, visual renderings, and speech synthesis and analysis. All of these problems are solved using highly arithmetic intensive algorithms. As a result, there is a growing demand for energy efficient addition circuits. The frequency of the addition operation and the ubiquitous nature of adder circuits make a low energy adder critical to the future of low-power system design. In fact, it is conceivable that in a PDA lacking a power-consuming secondary storage medium, addition circuits would represent a considerable percentage of the overall power dissipation. Therefore, our second goal is the derivation of energy-efficient addition architectures.;Our last goal concentrates on improving the performance of the random logic circuits which do not fit under the categories of either arithmetic or memory circuits. Aside from being fast, the logic should not dissipate power during periods of inactivity. To these ends, we propose a CMOS circuit technique which is faster than both conventional static and dynamic techniques. Since reducing a chip's supply voltage is essential for low-power design, circuit designers must compensate for the resulting loss in speed. Simply changing the circuit type of each boolean gate has only limited advantages. What is needed are circuit techniques which can merge several small gates together into one large high speed gate. We propose one such logic family for use along critical paths in complex circuits.