Research Of Driver Pre-emphasis Techniques For On-Chip Global Buses

With the development of SOC designs, more and more functionality isintegrated into a single chip. The complexity of the system on a chipdemands a higher requirement of on-chip interconnect bandwidth andreliability. With sub-micron process scaling technology, global interconnectbecomes increasingly important in determining the speed and power ofintegrated circuits. The performance of global interconnect has become thebottleneck for high-speed data communications.The thesis mainly focuses on the driver pre-emphasis architecture ofon-chip interconnect, which aims to improve the interconnect channelbandwidth and eliminate inter-symbol interference by emphasizing thehigh-frequency components while attenuating low-frequency ones. Theresearch work showed that the delay in pre-emphasis circuit structure has asignificant impact on circuit performance. Laplace transform was appliedto analyze the frequency response curve, thus obtaining the optimal delayfor circuit performance. The simulating environment is an interconnectwith the length of10mm under90nm process.Experimental results showed a better performance when applying ouroptimal delay parameter. Specifically, the under10-10part of BER for outputsignal was38.9%for conventional wire and56.3%for capacitively drivenwire. Therefore, the optimized pre-emphasis circuit could effectivelyimprove the transmission bandwidth.