The Research And Implementation Of Early Power Estimation Model Of FPGA

Field programmable gate array (FPGA) has been widely used in the IC industry since its advantage of low design cost and reprogrammable. With the IC process technology into nanometer size, FPGA integration is getting higher and higher, leading to the power consumption problem of the design is more prominent. Commercial FPGA power estimation tools including Xpower and EPE, which Xpower estimate power consumptionin the layout, and the results are accurate while EPE estimate power consumption in the early design with low accuracy. Other power evaluation research is carried out at different levels, remaining the problem of low accuracy.In this thesis, the early evaluation of FPGA power consumption is modeled and implemented. Based on introducing the FPGA architecture and power source, considering the complexity of the circuit structure of commercial FPGA, this thesis evaluate power consumption after complete of synthesis. FPGA power consumption can be divided into programmable logic resources and clock/interconnect power consumption, and modeled separately. For the programmable logic resources, a dynamic macro cell power consumption model based on switch activity and resource usage is established. After designing the random excitation generator based on ARMA signal, this thesis uses the method based on the probability of transmission to assess the activity of the circuit, then write perl script to analysis the netlist to obtain the usage of resources. For the clock/interconnect part, based on analyzing single interconnect power linear increased with module distance, a switch level power model based on area estimation is established. During this time, in order to extract the equivalent capacitance of different types of interconnects, a method based on difference and nonlinear curve is adopted.In addition, in order to verify the correctness of power consumption model, this thesis builds a simulation platform to evaluate the power consumption of Virtex-6 XC6VLX760 chip. The platform reads the netlist and the excitation signal, calculating the circuit node switch activity and the usage of resources. The 20 benchmark circuits of MCNC are compared with the results of Xpower software, the minimum error of the model is 3.62%, the maximum error is 45.3% and the average error is 22.8%. In the case of the same level of abstraction, compared with the similar model,this thesis has a higher accuracy of 23%, comparing with the similar model, which shows that the power consumption model can accurately assess the power consumption.