Phase-locked loop with adaptive supply noise cancellation

Phase-Locked Loops are widely used in high-performance digital systems to generate well-timed clocks. The timing uncertainty in the PLL's output clock limits the system performance. One of the dominating noise sources in the PLLs is the noise of the power supply. The switching activities of digital blocks contribute a large amount of noise on the supply lines in the digital systems.; This dissertation presents the design and implementation of a PLL system with adaptive supply noise cancellation. The PLL system effectively cancels the supply induced jitter at the PLL output with very low power and area overhead.; The PLL is designed with a programmable supply noise cancellation circuit and a fitter measurement system. A minimization algorithm can effectively program the cancellation circuit for the best jitter performance of the system. The proposed PLL along with the jitter cancellation circuits can reduce the supply induced jitter by more than 11 dB.