Research And Design Of CML Clock Buffer With Low Additive Jitter

In the age of information,the explosive growth of data transmission rate makes the high-speed link system put forward strict requirements on the clock buffer chip,including high working rate,strong driving ability and high matching characteristics.However,the jitter introduced by the clock buffer itself reduces the clock accuracy,which reduces the performance of sampling circuits that use clock signals,such as highspeed wired transceivers and data converters.This requires high demands on the lowjitter characteristics of the clock buffer.Based on this application,this paper selects CML clock buffer as the research object firstly,and then studies and designs a 1:2 highspeed low-jitter CML clock buffer.Meanwhile,to solve the problems of multiple power rails and power noise,a high power supply noise rejection(PSR)low dropout linear regulator(LDO)is designed in this paper.The main research contents and results of this paper are as follows:1.In order to meet the demands of low additive jitter in CML clock buffer,this paper presents theoretical dervation and verification of main source of additional jitter in CML clock buffer is analyzed in detail: thermal noise induced jitter,flicker noise induced jitter and power supply induced jitter.It is observed that the thermal noise induced jitter and flicker noise induced jitter are related to the size of the tail current and the size of tail transistor respectively,while the power noise induced jitter is mainly determined by the power noise.Assuming a perfect power supply,the big tail current and big tail transistor can reduce the impact of the jitter source.At the same time,to control additive jitter accurately,a design guideline for low jitter CML clock buffer is provided.2.Based on 0.18 um Si Ge Bi CMOS technology,a 1:2 high-speed CML clock buffer with low-jitter is designed in this paper.The system architecture,the design scheme of each sub-module and the specific circuit parameters are determined by analysing the design specifications.After the completion of the schematic,layout and the post-layout simulation,the CML clock buffer is taped out and tested.Under the condition of 3.3V power supply voltage and 8GHz,200 m V input wave,the measured results show that the differential output swing is 884 m V,the rise time is 42.3ps,the fall time is 38.6ps,the channel-channel skew is 5.4ps,and the additive jitter is 46.39fs(622MHz @ 12K～20MHz).They all meet the design specifications.3.In order to overcome the complexity of the traditional feedforward path,a simple feedforward path based on feedforward noise cancellation technology is proposed in this paper,which greatly reduces the circuit complexity.The feedforward path not only improves the PSR performance of LDO,but also improves the stability of LDO.Based on 0.18 um BCD technology,a high PSR LDO is designed in this paper.The post-layout simulation with layout parasitics is completed.The post-layout simulation results show that the quiescent current is 445 u A.At 0 load current,the LDO achieves PSR of-98.16 d B and-96.04 d B at DC and 1MHz.At 100 m A load current,the LDO achieves PSR of-101.45 d B d B and-80.40 d B at DC and 1MHz.The output noise of LDO is 25.63 u V RMS from 10 Hz to 100 KHz.They all meet the design specifications.