CMOS oversampling D/A conversion for ADSL central office modems

Asymmetric digital subscriber line (ADSL) technology has emerged as a practical means of providing for the high-speed transmission of data over standard telephone lines. The delivery of low-cost ADSL integrated circuits requires the integration of high-resolution data converters and analog filters with digital signal processing circuitry in CMOS technology. This integration requires high-performance analog circuitry to be implemented in a process technology that has been optimized for digital circuit performance. While advances in CMOS fabrication technology have resulted in the ability to integrate exponentially increasing amounts of digital computational power onto a silicon die, these advances have not generally resulted in performance gains for analog circuits. This dissertation explores the design of oversampled digital-to-analog (D/A) converters for ADSL central office modems. ADSL performance requirements are met through a careful digital and analog filter partitioning that leverages digital signal processing in order to simplify the required analog circuitry.; ADSL transceivers commonly employ segmented, current-mode D/A converters that achieve more than 80 dB dynamic range. These D/A converters typically use laser trimming, continuous current source calibration, or have been designed to intrinsically achieve the required resolution with careful attention to segmentation, switching algorithms, and layout techniques at the cost of area, wiring, and analog circuit complexity.; Oversampling and sigma-delta noise shaping can be employed to achieve high resolution with a low resolution D/A converter. However the use of sigma-delta noise shaping can place stringent requirements on the reconstruction filter to ensure adequate suppression of out-of-band quantization noise. This dissertation introduces an oversampled D/A converter in which digital and semi-digital filtering are employed to alleviate the complexity of the analog reconstruction filter. The design features the use of a multi-bit digital sigma-delta noise shaper and a multi-bit semi-digital reconstruction filter that employs data weighted averaging and a resampled impulse response. A digital pre-emphasis filter is used to compensate for the noise shaping and analog filter droop.; An experimental prototype has been integrated in a 0.18mum CMOS technology. When sampling at 200 MSample/s, the converter achieves 86 dB dynamic range for a 1.1-MHz bandwidth, with an average multi-tone power ratio of 65 dB.