| This work involves the development of digital calibration techniques for Analog-to-Digital Converters. According to the 2001 International Technology Roadmap for Semiconductors, improved ADC technology is a key factor in the development of present and future applications.; The switched-capacitor (SC) pipeline technique is the most popular method of implementing moderate resolution ADCs. However the advantages of CMOS, which originally made SC circuits feasible, are being eroding by process scaling. Good switches and opamps are becoming increasingly difficult to design and the growing gate leakage of deep submicron MOSFETs is causing difficulty. Traditional ADC schemes do not work well with supply voltages of 1.8V and below. Furthermore, the performance required by present and future wireless and IT applications will not be met by the present day ADC circuits techniques.; Bearing in mind the challenges associated with deep sub-micron analog circuitry a new calibration technique for folding ADCs has been developed. Since digital circuitry scales well, this calibration relies heavily on digital techniques. Hence it reduces the amount of analog design involved. As this folding ADC is dominated, in terms of both functionality and power, by digital circuitry, the performance of folding will improve when implemented in smaller geometry processes.; An 8-bit, 500MS/s, digitally calibrated folding ADC was designed in TSMC 0.18microm. A second prototype, 9-bit 400MS/s, was designed in ST 90nm. This ADC uses novel folders to reduce thermal noise.; The major accomplishments of this work are: (1) The creation of a new folding ADC architecture that is digitally dominated allowing large transistor mismatch to be tolerated so that small devices can be utilized in the signal path. (2) The development of modeling techniques, to investigate and analyze the effects of transistor mismatch, folder linearity and redundancy in ADCs. (3) The design of a new folder circuit topology that decreases the required power consumption for a given noise budget. (4) The design of a resistor ladder DAC that uses a unique resistor layout to allow any shape ladder to be designed. |
