Power optimization of algorithmic analog-to-digital converters

The dissertation presents techniques for power optimization in algorithmic analog-to-digital converters (ADCs) enabling realization of ultra low power data converters. Implantable biomedical devices and autonomous wireless sensor networks are among the most rapidly growing applications that require low speed, medium resolution ADCs. Traditionally, successive approximation register ADC architectures have been used for low power data conversion. However, the successive approximation architecture suffers from limited resolution and design flexibility. The dissertation shows algorithmic ADCs are a better architectural choice for the above mentioned applications due to its compact layout and its inherent re-configurability.; The dissertation shows the transfer of design complexity from the analog to the digital domain in algorithmic ADCs enables power optimized designs. Use of digital calibration reduces the amplifier design specifications, thereby saving power, at a minimal cost of increase in digital power dissipation. The amplifier slew rate is controlled digitally, further reducing the amplifier power dissipation. Additionally, a CMOS inversion coefficient design methodology is shown to optimally realize the reduced amplifier specifications for a given power budget.; The proposed techniques are experimentally verified using a 10-bit, 500 kS/s algorithmic ADCs fabricated in a 0.5-mum bulk CMOS process. Measurement results indicate that the proposed design techniques show a power savings of more than 70% compared to standard algorithmic ADC design.