Circuits and systems for wireless concurrent communication

Concurrency is a special kind of analog circuit parallelism that uses a single circuit with necessary bandwidth to process multiple signals at the same time. Concurrent radios offer a higher data rate and improved system diversity. Our comprehensive treatment comprises proposals for potential transceiver architectures, invention of circuit blocks, and provisions of innovative analysis methods.;The analysis of concurrent circuits are often complex. To simplify noise analysis, a R.;(N.;2 )-vector space is first proposed to re-formulate the N-portnetwork noise modeling problem. Any internal physical source inside the noisy network contributes a small vector in the defined R.;(N.;2)-vector space, andthe aggregate statistical behavior of this noisy network can be viewed as the vector sum of these vectors. Applying this concept to FET noise modeling leads to several modified FET noise models, in which three uncorrelated noise sources are sufficient to describe the statistical behavior of an intrinsic FET. The use of these new FET models can simplify the analysis, simulation, and optimization of low noise systems without sacrificing accuracy.;Broadband low-noise amplifier is a critical block in concurrent receiver systems. We propose a novel low-noise weighted distributed amplifier (WDA) topology, which uses the internal finite-impulse-response filtering inside a conventional distributed amplifier to partially suppress internal thermal noise. A distinct advantage of this topology is its tolerance to input parasitic capacitance which can be used to provide good electro-static discharge (ESD) protection without sacrificing its noise performance and power consumption. A compact 3.1–10.6 GHz WDA IC is built on a 130 nm CMOS process. Experimental results show 2.3–4.5 dB NF at 23 mW power consumption.;Using concurrency in wireless link can boost communication data rate. As a proof-of concept, we propose dynamically scalable concurrent communication by dividing the 7.5 GHz bandwidth of the unlicensed 3.1–10.6 GHz spectrum into seven concurrent channels. A CMOS octa-core RF receiver is implemented to validate the idea. Based on the receiver measurement results, a wireless link can be built to achieve a 16 Gbps channel limit at five meter TX-RX distance at 400 mW power consumption.;Tunable concurrency can improve the receiver diversity. A prototype 6–18 GHz concurrent tunable dual-band phased array receiver element IC is proposed and built on a 130 nm CMOS process. Experimental results demonstrate successful dual-band RF reception within a low band (6–10.4 GHz) and high band (10.4–18 GHz) with 300 MHz baseband bandwidth. A final four-element phased array receiver built from the prototyped ICs shows an array pattern with worst-case 21 dB peak-to-null ratio across all frequencies.;Concurrency can also be used to achieve multi-beam reception by providing multiple phase-shifts for each RF signals and combining them separately at baseband outputs. A 10.4–18 GHz concurrent dual-beam phased array receiver is proposed based on this concept, and is implemented on a 130 nm CMOS process. A final four-element phased array system shows successful concurrent dual-beam reception at the same RF frequency.