| The dissertation presents a 4-channel phased array receiver front-end in 0.13 mum CMOS operating in the 24 GHz band. The chip has low power consumption and a small area and is a good candidate for a high-performance wireless communication systems. The dissertation includes the design of 24 GHz CMOS LNAs, demonstration of a 6-bit phased array receiver channel, study of on-chip coupling effects, implementation of a differential phased array receiver with on-chip baluns, and 24 GHz packaging and board design.;In the 24 GHz LNA design, a common-source (CS) LNA, a common-gate (CG) LNA and a cascode LNA are discussed and compared. A nearly simultaneous noise and power match for a CG LNA at 24 GHz is explained. A CS-cascode-cascode 3-stage LNA and a CG-cascode-cascode are implemented.;The 6-bit phased array receiver channel introduces an active phase shifter with a novel active vector generator and results in a 6-bit phase response at 23--24.5 GHz and a 5-bit resolution at 20--28 GHz.;The on-chip coupling study shows that the dominant coupling components result in system-level gain and phase errors, and the coupling component increases as G2 while the signal component increases as G. It is recommended that the additional gain be placed after the RF combiner node or a differential topology be used for LNAs if a high gain is need for the phased-array system.;The differential phased-array receiver chip shows a measured gain of 12--15 dB at 24--27 GHz, a measured NF of 7.8 dB at 25 GHz, a measured S11 and S22 < --0 dB at 24--27.4 GHz, measured rms gain and phase errors of < 0.5 dB and < 5.6° at 23.5--26.5 GHz, respectively, measured input P 1dB and IIP3 of --22 dBm and --12 dBm, respectively, measured rms gain and phase coupling errors < 0.3 dB and < 2° at 21--30 GHz, respectively, and measured channel-to-channel rms gain and phase mismatches of < 0.5 dB and < 4° at 20--30 GHz, respectively, and has a total power of 230 mW and a dimension of 1.8 x 2.2 mm2. To our knowledge, this represents state-of-the-art results not yet achieved using CMOS at this frequency range. |
