Research Of Low Noise Amplifiers Based On Silicon Technology

With the rapid development of information technology,the performance of wireless communication system,such as phased array radar,WiFi,Bluetooth,and GSM/CDMA/LTE,is increasing demanded.Nowadays,the wireless communication system is developing towards high performance,low cost and high integration.As a key module in the RF analog front end of the wireless communication system,the performance of the low noise amplifier(LNA),such as noise figure,power gain,linearity and VSWR,has a direct impact on the whole system.Due to the advantages of low cost and high integration,the research of LNA based on silicon process has become a hot topic in the RF field.And it is significant for the development and applications of high performance and low cost wireless communication products.Based on the research progress and development trend of LNAs manufactured in silicon process,the design technology for LNA was highlighted in this work.The noise performance of HBT in Si Ge BiCMOS process and NMOS fabricated in CMOS technology was discussed,and the circuit topologies and design methods were also analyzed and studied.There were mainly two sections described in this thesis according to the research work.Firstly,a low noise amplifier applied to Ku band phased radar system based on IBM 0.18?m SiGe BiCMOS process was designed.A two-stage common-base common-emitter(cascode)topology was adopted for the requirements of LNA.The first stage was optimized for the noise performance,while the second stage was applied to improve the power gain and the linear output power.In order to improve linearity,a linear compensation bias circuit was introduced with considering of the rectification of HBT,which does not increase the chip size and complexity.The simulation results shown that the noise figure of designed LNA is less than 4dB,the power gain is greater than 22 dB with a supply voltage of 3.3V.When the LNA operates at the frequency of 16.5GHz,the output power of 1dB compression point is higher than 6.5dBm.Compared to the LNA with conventional bias circuit,the output of 1dB compression point in this work is doubled.Additionally,considering the characteristics of TD-LTE,several noiseoptimization methods for LNA based on the CMOS process were analyzed and discussed.And a method to achieve simultaneously the noise and power matching was proposed under the constraint of power consumption.A two-stage LNA with cascode structure based on UMC 0.18?m CMOS process was designed.And we had completed the circuit schematic design,layout and tape-out.The simulation results shown that the noise figure is less than 2.2dB,the power gain is greater than 25 dB,and the input/output ports have perfect match between the operating frequencies of2575-2635 MHz with a supply voltage of 1.8V.