| Phased array systems are widely used in modern 5G,satellite communications and active electronically scanned array(AESA)radars,and have many advantages,such as wide bandwidth and wide-angle scanning.A typical phased array system includes a radiation unit,a transmitter/receiver module,an RF beam combiner,and other control and power modules,among which the transceiver module at the front end of the phased array system is mainly used to realize the signal transmission and reception,amplification and amplitude phase,which is the most important of the entire system.The design of the module chip is generally realized by using III-V compound process or silicon-based process,both of which have their own advantages and disadvantages.The III-V compound process has better temperature characteristics and can achieve lower noise figure and high power capacity;The CMOS process has low cost,and with the continuous development of the process,the characteristic frequency is continuously improved,and it is increasingly used in the design of radio frequency microwave integrated circuits.In order to achieve high-precision amplitude control and low-noise signal amplification,this article will conduct a detailed and in-depth study on these two functional modules.First,based on the SMIC 55 nm CMOS process,several core modules of multi-function chips are designed and implemented;secondly,a variable gain amplifier is designed based on the Ga As 0.5um ED mode p HEMT process.The specific work is as follows:1.In order to solve the problem of the amplitude control of the multi-function chip,a silicon-based passive attenuation technology is proposed,which adopts a digital control method with a step of 0.5dB.This research mainly conducts theories on the T-type,bridge T-type and Pi-type of the attenuation unit Analyze and combine specific chip design practices to select a reasonable switch device size to achieve lower attenuation error and insertion loss.In order to solve the problem of large additional phase shift when the attenuator is working,phase compensation technology is adopted.Parallel an LPF(low-pass filter)structure with phase lag on the branch or parallel capacitors or MOS transistors in the cut-off state on both ends of the resistors on the parallel branch.The final additional phase shift at room temperature is between -6°?3 In order to solve the requirements of the chip for temperature characteristics,the attenuator is temperature compensated by resistors with different temperature coefficients,so that it can meet the index requirements at -55??125?.The final simulation result shows:attenuator The attenuation root mean square(RMS)error is less than 0.55 dB.The measured results show that the attenuator is working normally,and some indicators need to be adjusted.2.In order to solve the system's requirements for high and low temperature gain fluctuations,a temperature compensation attenuator is proposed.By providing voltages with different temperature coefficients to the gates of the series MOS tube and the parallel MOS tube,the insertion loss at high temperature is small,and the low temperature When the insertion loss is large,the gain of the system at high temperature and low temperature can be shortened.The simulation results show that the insertion loss at -55? is-6.7dB,the insertion loss at 25? is -5.4dB,at 125?.The insertion loss at ? is-3.8dB.As the temperature increases,the overall insertion loss decreases uniformly,which has the effect of temperature compensation.3.In order to avoid the degradation of the SNR of the multi-function chip receiving channel as much as possible,a LNA is designed as the first module.Its noise figure can be said to play a decisive role in the entire system.And the higher the gain,the smaller the influence of the noise of the subsequent module on the circuit.This low-noise amplifier adopts two-stage cascode,the first stage focuses on noise performance,and the second stage pays more attention to gain characteristics.This design method can achieve both Low noise and high gain,the final simulation results show: at 32GHz-38 GHz,NF is less than 3.81 dB,Gain is greater than 16 dB,High consistency between measured results and simulation.4.The insertion loss of the passive attenuator will increase the gain pressure of the system,and an additional amplifier is needed for loss compensation.To solve this problem,the variable gain amplifier is studied.The module has a positive gain while controlling the amplitude.,Is mainly achieved by cascading amplifiers and attenuators.Considering that the final chip needs to be packaged,which help improve the accuracy of the simulation,the gold wire model is modeled and EM simulated in HFSS,and the S parameter descendants are extracted Enter the schematic diagram for joint simulation and optimization.The final simulation results show that the amplitude control error of the variable gain amplifier is less than ± 0.5dB at 0.1GHz-6GHz.When the attenuator is in the ground state,the overall noise figure is less than 5.5dB,and OP1dB is greater than 18 dBm,the test results show that the amplifier and attenuator are working normally,but some indicators have deteriorated. |
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