Closing the gap between FPGA and ASICS: The applications of clock skew scheduling on FPGAS

Since the first field programmable gate arrays (FPGAs) production in 1985, were used only as glue logic, FPGAs have dramatically improved to compete with application specific integrated circuits (ASICs). Even entire system on chip (SOC) designs can now be built on an FPGA. In addition, today's trends in shorter life cycles of products, and exponentially increasing costs of the mask and NRE with shrinking process technology make FPGAs the preferred design solutions over ASICs due to the advantages of faster time to market, field reprogrammability, and low non-recurring engineering (NRE) cost. However, the advantages of FPGAs, which have been brought by reconfigurable nature of FPGAs, come with the cost of slower speed, higher power consumption, and larger device size. Since FPGAs must use more transistors and interconnects than ASICs for the same functionality.;To reduce the performance and power consumption gaps between FPGAs and ASICs, which are limiting factors of further widespread use of FPGAs, FPGA vendors have aggressively adopted the latest process technology with innovative FPGA architectures. Besides the hardware-wise optimizations, FPGA Computer Aided Design (CAD) tools also have been improved to have state-of-the-art capabilities to optimize logic designs through various stages of the CAD flow. However, even with the optimization efforts, FPGAs are still considered to have 2∼3 time slower performance and 2∼5 times more power consumption than ASICs [1].;In this dissertation we propose clock skew scheduling FPGA architectures and optimization CAD algorithms effectively leveraging timing slacks in the logic designs for various design optimization goals to reduce the gaps further. We first study issues in implementing a clock skew scheduling technique on an FPGA and possible solutions for the issues, and develop a clock skew scheduling FPGA architecture and an optimization CAD flow to enhance performance of logic designs by resolving some of the issues. We then develop a low power body biasing FPGA architecture and an optimization CAD flow, where power reduction is enhanced by a clock skew scheduling technique. Finally, we study a temperature-variation adaptable FPGA architecture and an optimization CAD flow to minimize performance degradations due to thermal timing margining for reliable operation under harsh environments.