Structural delay testing of latch-based high-speed circuits with time borrowing

Latch-based circuits are used in full custom designed high-speed chips, especially to implement some delay critical parts due to two benefits: higher performance and higher yield at desired performance. However, the unavailability of a delay test methodology that provides sufficiently high coverage has hindered their widespread use.;In this dissertation, we show that the conventional delay testing approaches cannot be used for delay testing of latch-based circuits with time borrowing, and show that it is necessary to use design-for-test (DFT). We first focus on maximizing path delay fault coverage and propose the first path delay testing approach and the associated DFT for such circuits. We prove that our latch-based delay testing approach provides the theoretical maximum coverage (for any scan-based approach). We also prove that this coverage is always greater than (or equal to) that for the latch-based circuit's flip-flop-based counterpart. Secondly, we focus on minimizing test application cost for delay testing latch-based circuits under the constraint that maximum coverage is achieved. We show that conventional test scheduling methods may not be applicable due to the unique characteristics of latch-based circuits with time borrowing. We then formulate the minimization problem and propose a deterministic and two heuristic approaches for test scheduling of such circuits.;The experimental results show that, for many example circuits, the proposed approaches achieve dramatically higher coverage of path delay faults compared to classical approach, and achieve test application costs that are within 5% of the corresponding lower-bounds.;We then compare high-speed latch-based circuits with their flip-flop-based counterparts from the viewpoint of path delay testing and present design guidelines for latch-based circuits that guarantee that latch-based circuits also achieve higher yield and higher performance than their flip-flop-based counterparts.