Design Of Low Voltage Low Power Super High Speed Integrated Circuits Based On 0.18μm CMOS Process

Several characteristics and trends, such as network, digital, intelligence and low power present during the innovation and development of IT industry. High speed, broad band communication network are required to communicate information. For these reason, Optical communication will gradually replace cable communication. In optical transmission system, Demultiplexer(Demux) is at the tail end of the optic-fiber receiver. Demux transforms the one way high speed serial signal which from data decision to N (N>1) way low speed parallel signal. Therefore, Demux is an important part of high speed communication system, its performance directly influence the last output signal. So, high speed Demux circuit is the indispensable key circuit in optical communication. Additionally, super high speed frequency dividers are widely applied in optical communication and wireless communication system. In a Demux, frequency divider converts the high speed clock to the lower speed clock. In the case, frequency divider is one of the circuits working on the highest frequency. With the development of CMOS process, design of super high speed frequency divider based on CMOS process makes great sense.The article's main objective is to analyze, research and realize a super high speed frequency divider circuit based on 0.18μm CMOS process, and the circuit's work rate is over 20GHz.And based on the same process, analyze, research a low voltage, low power 1:4 Demux applying for STM-64, the chip will be sent to foundry in the next MPW project, and subsequently be tested on wafer. Since the standard voltage in 0.18μm CMOS process is 1.8V, and f t is 49GHz, in 1.2V, traditional circuit structures are hard to work up to 10Gb/s, similarly, the traditional ones in 1.8V power supply are hard to work up to 20GHz.In order to achieve the unification of low voltage, low power and super high speed, the article applies an improved common-gate structure dynamic load latch. Based on this latch, design and realize a 1:4 super high speed frequency divider in TSMC 0.18μm CMOS process.On-wafer experimental results show its highest work rate can be up to 26GHz, and its work range is over 20GHz; Package experimental results show the chip can work up to 19.6GHz and performs well in 10GHz which is the desired work rate. The article also accomplishes the simulation and layout design of a 1.2V 10Gb/s 10mW 1:4 Demux based the same process, the chip will be sent to foundry in the next MPW project, and subsequently be tested on wafer.The article presents the basic principle of Demux and frequency divider, and describes the design flow in detail by the sequence of circuit design, layout design and chip test. Finally, the paper gives the test results of the 1:4 super high speed frequency divider. The on-wafer and package measurement results of the chipset show that the low voltage, low power, super high speed frequency divider works well and totally meet the task of the design. The chip has the bright future in industrialization.