Digital circuit methodologies for low power and robust nanoscale integration

The integration density and the operating speed of integrated circuits are enhanced with technology scaling, thereby leading to broader functionality and enhanced performance The advantages of technology scaling, however, come at a cost of elevated power consumption and enhanced sensitivity to parameter variations. Developing low power and variation tolerant integrated circuit techniques has become a primary necessity for the semiconductor industry.;The multiple supply voltage circuit techniques exploit the delay differences among the different signal propagation paths by lowering the supply voltages of the gates on the non-critical delay paths while maintaining a higher supply voltage on the speed critical paths. Specialized voltage interface circuits are required in order to transfer signals among these circuits operating at different voltage levels. New low-power and high-speed multiple threshold voltage interface circuits are proposed to enhance the efficiency of the multiple supply voltage techniques.;The clock distribution network consumes a significant portion of the power, area, and metal resources of an integrated circuit. The enhancement of clock frequency and the increased number of clocked elements cause the power consumption of the clock distribution subsystem to increase significantly. Furthermore, the parameter variations are enhanced with each new technology generation. Novel clock tree design methodologies are proposed for simultaneously suppressing the temperature fluctuations induced skew and the power consumption of clock distribution networks.;The reduced supply and threshold voltages and the scaled device dimensions lead to a degradation in the data stability of memory banks with technology scaling. The increasing leakage energy consumption of memory caches is another important concern. New circuit techniques are proposed for simultaneously enhancing the data stability and reducing the leakage power of nanoscale memory banks.;Scaling of the single-gate MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage currents and enhanced sensitivity to process variations. Multi-gate FinFET technologies mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. FinFET technology development guidelines are proposed. New low power and robust FinFET static memory circuits, sequential circuits, and domino circuits are proposed.