Semiconductor flash memory scaling

Semiconductor flash memory is an indispensable component of modern electronic systems. The minimum feature size of an individual CMOSFET has shrunk to 15mn with an equivalent gate oxide thickness (EOT) of 0.8nm in 2001. However, semiconductor flash memory scaling is far behind CMOS logic device scaling. For example, the EOT of the gate stack in semiconductor flash memory is still more than 10nm. Moreover, semiconductor flash memory still requires operation voltage of more than 10V, while the operation voltage of CMOS logic has been scaled to 1V or even less.; This dissertation addresses the issue of gate stack scaling and voltage scaling for future generations of semiconductor flash memory, and proposes solutions based on new memory structure and new materials that are compatible with the current CMOS process flow. Chapter 1 discusses the key challenges in scaling flash memories. In chapter 2, a theoretical model that accounts for both the Coulomb blockade effect and the quantum confinement effect is proposed to model semiconductor nanocrystal memory. The program/erase speed and retention time in terms of nanocrystal size, tunnel oxide thickness, and different tunnel material other than silicon oxide has been investigated. Semiconductor nanocrystal memory is shown to have the potential to replace the conventional floating gate flash memory. Chapter 3 demonstrates that high quality silicon nitride can be used as the tunnel dielectric to enhance the programming speed, since it offers a low injection barrier as compared to silicon oxide tunnel dielectric. Retention time is also enhanced due to the fact that thick tunnel nitride can be used for the same EOT. In Chapter 4, Hafnium oxide was investigated to replace silicon nitride as the charge trap/storage layer in SONOS (silicon-oxide-nitride-oxide-silicon) type trap-based memory. Since the conduction band offset between Hafnium oxide and tunnel oxide is larger than that between silicon nitride and tunnel oxide, the tunnel barrier from the charge trap layer is reduced/eliminated during programming; fast programming speed was achieved with Hafnium oxide trap layer experimentally. The large conduction band offset can also improve the retention time. New device structures are also indispensable in making flash memory more scalable. In Chapter 5, a FinFET SONOS flash memory device has been demonstrated. Its channel length is scalable to 40nm. The experimental results showed that the FinFET SONOS memory exhibited good program/erase speed, high endurance and good reading disturbance. It is a suitable embedded memory for the future FinFET circuit. FinFET memory can achieve a much smaller cell size than that predicted by ITRS roadmap.