Research And Design Of Low Power Readout Circuit For Computing-in-memory Chip

The Computing-In-Memory(CIM)chip based on non-Von Neumann architecture shows unique advantages in the field of processing Convolutional Neural Network(CNN)algorithms.The core component of this architecture is the CIM cell array,consisting of the CIM devices.The input,processing and output signals of the CIM cells are all analog signals.The readout circuit is designed to sample and quantify the calculation results that are output in the form of current by CIM cells.The CIM chip is intended to break the bottleneck of the memory access power wall caused by the Von Neumann architecture.The CIM array and readout circuit in the CIM architecture chip have high-density parasitic load,the research and design of the low power readout circuit for the CIM chip has become an important topic.The low power readout circuit studied and designed in this paper includes two core modules: a current sampling conversion module and an Analog to Digital Converter(ADC).The flow of the readout circuit consists of two main steps: the current sampling conversion circuit samples and converts the output currents of the CIM unit into voltages,and the ADC quantifies the outputs.The main contents of the paper are as follows:First,this paper study the application fields of the CIM chip and the CIM architecture.In the CNN algorithm,more than 90% of the operations are matrix multiplication or addition operations.Chips based on the CIM architecture can efficiently implement these mathematical functions in the CIM devices.The readout circuit is designed to quantify and output the calculation results of the CIM cells.The accuracy,speed,power and area of the readout circuit affect the calculation accuracy,energy consumption ratio and integration of the CIM chip.Considering the requirements of CIM for the readout circuit,a readout circuit architecture based on a new type of current sampling conversion circuit and a low power Successive Approximation Register(SAR)ADC is proposed.Next,the design of the new current sampling conversion circuit is carried out.The current sampling conversion circuit,as a core module in the readout circuit,is designed to sample the current signals of the CIM cells and perform the current-to-voltage conversion.The current sampling conversion circuit designed in this paper has the following innovations:it can provide a stable clamping voltage for the output terminal of the CIM cells and perform high-precision current sampling;it eliminates the error caused by the device in the copy circuit close to the cut-off area,supports the current-to-voltage conversion of the ground rail output in a single power supply system,and the next-stage ADC does not need to introduce the reference voltage and buffer circuit to eliminate the Direct Current(DC)bias;the DC bias realizes multi-range voltage output through the switch network in the control circuit,and can match the dynamic range of the ADC according to the data sparsity of the CIM cells.The current sampling conversion circuit designed in this paper is benefit to large-scale array integration,and the power consumption is mainly determined by the output current of the CIM cells.Next,an 8-bit 5 MS/s SAR ADC is designed.The SAR ADC,as another core module circuit in the readout circuit,is designed to qualify the analog output voltages of the current sampling conversion circuit into the digital signals,which completes the reading of the signals from the CIM unit.In the SAR ADC circuit,sampling switches,comparators,and Digital to Analog Converter(DAC)capacitor arrays are implemented based on the analog circuit design methods.The SAR ADC circuit utilizes a switching circuit with bootstrap capacitor to eliminate the distortion problem of original input signals which are sampled and held;it utilizes a comparator with a wider dynamic input range,introducing a pre-amplification stage and a latch structure,reducing the offset and power overhead of the SAR ADC;it utilizes the capacitor upper plate sampling method is adopted to reduce the area of the capacitor array;the SAR control logic synchronizes the logic sequence to adapt to the application of different speeds.Finally,layout design and post-simulation verification of the readout circuit are conducted.The core area of the readout circuit is 80 ?m*90 ?m.Under 1.2 V power supply voltage,post-simulation results of the readout circuit with parasitic parameters are: the overall power consumption of the readout circuit is 85 ?W,the Signal-to-Noise and Distortion Ratio(SNDR)is 44.08 d B,and the Spurious Free Dynamic Range(SFDR)is 49.14 d B.The results show that the readout circuit has low power consumption,small area and high precision,which meet the application requirements of the CIM chip.