Research On The Key Techniques Of Digital Readout Circuit For Infrared Focal Plane Array

With the development of infrared focal plane array(IRFPA)in the direction of large-scale and high-resolution,the readout circuit(ROIC)of IRFPA is gradually developing towards digitalization,with more flexible working methods and more signal processing functions.Among them,analog-to-digital converter(ADC)integrated onchip is the most important.Integrating an ADC in the ROIC can avoid the interference introduced by the transmission of analog signals between chips,reduce noise,and increase the transmission speed of the signals.The realization of digital output on-chip also provides a basis for integrating more digital image processing functions in the ROIC in the future,which is an important direction of the development of digital IRFPA.In this paper,the key technology of the digital ROIC of cooled IRFPA is studied.The ROIC is incorporating analog-to-digital conversion,multi-function digital control module and high-speed transmission digital interface.This paper uses the Global Foundries CMOS 0.18?m 1P6 M 3.3/1.8V process to perform circuit schematic design and simulation,layout design and post simulation,tape out and verification.According to the low temperature(77K)working environment of ROIC,the cryogenic influence of MOSFET devices is analyzed,the cryogenic CMOS process parameters are extracted,and the BSIM3v3 simulation model is modified.Based on the modified cryogenic simulation model,the cryogenic simulation of analog circuits such as reference current source and integral input stage are completed.The system structure and specific algorithm of ADC integrated in readout circuit are analyzed.As the limitation of the pixel area of IRFPA,the structure of pixel level single slope integral ADC is determined to be incorporated in ROIC.In the single slope integral ADC,a continuous integral ramp generator is proposed to output high-linearity ramp voltage,and a two-stage open-loop comparator with mixed voltage source is designed to reduce power consumption with low change of the transmission delay which is less than 3ns.For the pixel-level ADC structures,the comparator and latch of ADC are integrated in the unit circuit,and the ramp generator and counter are shared as lines.A 14 bit ADC is designed,and the dynamic effective bit is 13.96 bit after simulation.In the design of the digital control module of the ROIC,a Gray code counter triggered by both edges of the clock is designed,which effectively reduces the counting period and improves the conversion rate of ADC,and is suitable for different counting lengths in digital control module of IRFPA of different sizes.The digital control module internally generates working timing,realizes multiple scanning modes of rows and columns,serial output of digital signals and output of test timing,improves flexibility and integration of IRFPA,and reduces the number of circuit ports.The interfaces of the input and output digital signals of the readout circuit adopt low voltage swing difference signal(LVDS)interface,and the transmission speed of the digital signals can reach 500 MHz.A test platform including software and hardware of digital ROIC is built.The ADC conversion rate is measured as 12.21 k S/s,and the 14 bit digital signal readout rate is 7.14 MHz at 100 MHz clock.At 77 K,the effective resolution of dynamic performance is 11.47 bit,the no-missing code resolution of static performance is 13.94 bit,the maximum differential nonlinearity is less than 1LSB,the maximum integral nonlinearity is less than 1.5LSB,and the minimum resolution voltage of the ADC at 2V range is 122?V.After interconnection with the infrared detector,the linearity of the readout circuit is more than 99.99%.The equivalent noise the readout circuit is 0.51 m V.The digital readout circuit incorporating a pixel-level single slope integral ADC is suitable for the signal readout of the infrared detector,which provides the technical basis for the development of digital readout circuit of the large array IRFPA.