Side Breakdown Technique And Novel Structures Of SOI Lateral Power Devices

The silicon-on-insulator(SOI)technique has been widely used in intelligent power applications because of the excellent isolation performance,high speed,low leakage current and strong anti-radiation.As the key part in SOI power Integrated Circuits,SOI lateral power deives have been the research focus of the researchers who works on the semiconductor devices.How to obtain a breakdown voltage over 600 V to satisfy the k V level voltage in power integrated circuits is an important issue.Increasing the breakdown voltage will also increase the specific on-resistance,therefore,the trade-off between the breakdown voltage and specific on-resistance is the major issue in the design of the SOI lateral power device.In this thesis,the novel structures and analytical models of the SOI lateral power devices are researched addressed the trade-off between the breakdown voltage and specific on-resistance.The high-k dielectric technology,the lateral drift region impurity density linearization technology and the field plate technology are extended from two-dimensional to three-dimensional,so as to obtain better device performance with a simpler manufacturing process.The following new types of SOI lateral power devices are designed and studied respectively.The analytical model is established for the corresponding devices.1.Novel structure and analytical models of the SOI lateral power device with side high-k dielectric.The new device is characterized by the alternate silicon pillars and high permittivity(HK)pillars in the drift region.The HK dielectric enhances the surface electric field,which leading to an improved breakdown voltage(BV).Meanwhile,the HK dielectric causes an enhanced self-adapted assistant depletion of the n pillars,which allows to keep a higher doping concentration of the n pillars and thus further reduces the specific on-resistance(Ron,sp).By solving the Three-dimensional(3D)Poisson equation,the analytical models of the surface potential and electric field distribution,breakdown voltage and optimal drift region doping concentration are established.The validity of the proposed model is verified by the fair agreement between the analytical and numerical results.The simulation results indicate that the SOI lateral power device with side high-k dielectric reduces the specific on-resistance by 43% in comparison with the conventional device,and its breakdown voltage and Figure of Merit(FOM)are 1.32 times and 3.1 times of the conventional device respectively.2.Novel structure and analytical models of the SOI lateral power device with with partial oxide pillars.The new structure is characterized by the alternate doped silicon pillars and partical oxide pillars in the drift region,which can be fabricated by the dielectric isolation process without any additional mask.Owing to the modulation of the oxide pillars,a new additional electric field peak is introduced in the middle of the drift region,which improves the breakdown voltage and reduces the specific on-resistance.By sectionally solving the 3D Poisson equation,the surface potential and electric field distribution models and breakdown voltage models are established.All the analytical results are verified by the numerical results.A good agreement between the analytical and numerical results is obtained.The triangle trench field plate is applied to the SOI lateral power device with with partial oxide pillars.The influences of device parameters on breakdown voltage and specific on-resistance are investigated.The simulation results show that the proposed device enables a 40% increase in breakdown voltage and a 65% decrease in specific on-resistance,the FOM of new device is 5.5 times of the conventional device.3.Novel SOI lateral power device with Variation of Lateral Width(VLW)Technique.VLW technique is a new concept to obtain the linear distribution of charge density in the drift region and flatten the lateral electric field to maximize breakdown voltage.According to the VLW technique,the SOI lateral power deive with linear graded drift region width and the SOI lateral power deive with step drift region width have been proposed.In the SOI lateral power device with linear graded drift region width,the linear increased lateral width of the silicon pillar results in an almost ideally uniform lateral electric field distribution and the highest breakdown voltage.Meanwhile,the high-k material is used into the dielectric region to reduce the specific on-resistance.The 3D simulation indicates that the breakdown voltage of the the SOI lateral power deive with linear graded drift region width exceeds 600 V,and the specific on-resistance is reduced by 50% in comparison with the conventional device with the same geometric parameters.Moreover,the FOM of new device is 10 times of the conventional deivice.In the SOI lateral power device with step drift region width,the drift region of the new device is divided into several regions with different width increasing from source to drain.New additional electric field peaks are formed at the steps,which modulates the electric field and enhances the breakdown voltage.The high-k material is used into the dielectric region for futher improving the performance of device.The analytical model of surface electric field is established to investigate the mechanism of the SOI lateral device with VLW technique.4.New analytical model for SOI lateral power device using variation of lateral thickness(VLT)technique The VLT technology has been proposed as an effective lateral voltage-sustaining technology.However,no analytical model has been reported for exploring the physical mechanism quantitatively.The analytical expressions for the surface potential and electric field distribution are established by solving the two-dimensional(2D)Poisson equation.The lateral and vertical breakdown voltages are formulized to quantify the breakdown characteristic.The drift doping concentration range is derived to maximize the breakdown voltage.This analytical model is used to investigate the electric field distribution and breakdown voltage of the VLT SOI device with various parameters.