Research On The Key Modules Of Low Power RF Receiver

With the cross rapid development of Internet of things,artificial intelligence and life sciences,Human beings are gradually entering into intelligent and information society.RF front-end module act as an important communication medium between electronic devices and the outside world,the performance of which directly determines the communication mode,quality,stability,standby time and other important performance indexes that electronic equipments can support.Due to the continuous development of semiconductor and communication technology,which encourages the RF front-end module to explore the area of UWB,UHF and ULP.LNAs,mixers and frequency sources are studied in this paper extensively and deeply.The main work and innovation as follows:1.Aiming at the disadvantages of high power consumption and low integration in most UWB LNA designs,this paper presents an UWB LNA with a great advantage in chip area and power consumption.The first stage and the second stage of the LNA circuit employ current reuse technology to reduce power by stacking transistors,and the first stage introduces inductor and feedback resistor to compensate parasitic capacitors,meanwhile realize gain flatness and input matching in the high frequency.The bandwidth of the LNA is from 2.8 to 10 GHz,the average power gain,the minimum NF,the power consumption,and the chip area are 13.2 dB,4.38 dB,6.54 mW,and 0.07 mm²,respectively.2.In view of the requirement of multimode,multiband and multifunction in wireless communication,this paper proposes a variable gain UWB LNA.The LNA adopts two-stage amplification structure,the first stage of the circuit utilizes the resistive feedback technology to realize the input matching with the inductive feedback technology,and introduces inductive peaking technology to achieve the gain flatness in high frequency.The second stage applies the common source amplifier structure to realize the variable gain by controlling the load impedance and the working state of the amplifier transistor.The implemented LNA can work from 3 GHz to 10 GHz with an input matching of S₁₁less than-9 dB.The power gain is continuously adjustable in range from-13.2 dB to 16.4dB.The minimum NF,the maximum power consumption and the chip area are 3.7 dB,16.2 mW,and 0.12 mm²,respectively.3.For the requirement of multiband,multimode function in modern communication system,this paper proposes a variable gain UWB mixer design.The circuit consists of common gate amplifier circuit and double balanced gilbert mixer circuit,and the gain variation is realized by changing the load in common gate amplifier circuit.Finally,the working band of the proposed mixer is 3-20 GHz,the conversion gain is 5.6-14.8 dB,the noise figure is 6.8-8.5 dB,the linearity IIP3 is better than 3 dBm,the isolation is better than 30 dB,and the power consumption is between 11.3-14.7dB.4.For the disadvantage of the low efficiency and low integration in UHF oscillators,this paper exhibits an oscillator design with an integrated antenna.The maximum power output theory is used to embed the active devices with the compensation network for the maximum power output,and the resonance circuit is realized with the GCPW to reduce the chip area.A broadband antenna is integrated in the oscillator ensuring the gain and efficiency.The static current consumption is 13.176 mA,the output power is 0.751 mW,and the DC-RF efficiency is 4.75%.5.With the requirement of low power consumption and low phase noise in high frequency PLL,a low power consumption integer frequency PLL structure for Ka band is proposed in this paper.The VCO obtain enough drive ability and isolation ability for the first frequency divider by introducting an output buffer stage.The divider part combines the CML dividers and logic gate dividers with a DTS module,which greatly reduces the design power.The PLL consumes 33.6 mW with a single 1.2 V supply including all the buffers.The phase noise of VCO reaches-105 dBc/Hz at 1 MHz offset,and the tuning range of VCO is 25.5-30.3 GHz.6.In view of the demand for high integration of crystal oscillator,two applied crystal oscillator are designed in this paper.OCXO circuit based on the B-mode suppression has been realized by the relevant theoretical analysis and simulation work,whose power consumption and phase noise have reached the performance level of relevant products on the market.In addition,LDO,divider and temperature control module are integrated into the chip,which greatly improves the integration of the OCXO,and beneficial to the various application scenarios.The measured parameters of TCXO can match the performance index of the current crystal oscillator set up by discrete devices.The integration of the crystal oscillator is greatly improved by integrating the LDO,frequency seletion network and buffer into the chip,and satisfies the demand of miniaturization.