Research On High Performance Wideband Phase-Locked Loop

With the rapid development of multi-standard 5G/6G communication,smart home,unmanned driving and other applications,phase-locked loop(PLL)chips on silicon with wide output frequency range,low phase noise,short locking time,and low output spur are key modules in wireless systems,while high integration and low cost are also key design requirements of PLL.However,with the continuous expansion and increase of operating frequency,the design of PLL and its key module oscillator still faces many challenges.In this dissertation,based on silicon CMOS technology,a series chips of high-performance oscillators and a new architecture of low phase noise highperformance PLL are proposed.The operating frequency covers RF,microwave,and millimeter-wave bands.The main contributions and innovations of this dissertation are mainly reflected in the following aspects:1.Low phase noise and high efficiency power oscillator.To solve the problem of low phase noise and high efficiency of power oscillator,an architecture combining a digitally controlled transistor array and a resonant network based on a high efficiency transformer is proposed,which supports digital programmable output power and frequency.Based on this architecture,a 2.3-2.86 GHz power oscillator was developed on 40 nm CMOS technology.The power oscillator achieves a figure-of-merit of 189.2d Bc/Hz and a peak efficiency of 25.1%.2.Millimeter-wave wideband quad-mode tail-current filtering oscillator.In view of the difficulty of realizing wide output frequency range and low phase noise in millimeter-wave oscillator,a quad-mode tail-current filtering is proposed.The electromagnetic hybrid coupling quad-mode mode switching technology is adopted to achieve the millimeter-wave wide output frequency.Besides,the quad-mode tail current filtering technology is used to reduce the phase noise.Meanwhile,the dual-coil in-phase coupling transformer is proposed to improve the quality factor of the resonator.Based on 40 nm CMOS technology,a wideband oscillator operating at 19-39.2 GHz is designed and integrated in the phase-locked loop.The phase noise of-132 d Bc/Hz@10MHz at 19 GHz is achieved.3.Millimeter wave wideband low jitter fast-locking subsampling PLL.In order to solve the problem that the dead zone of the frequency locked loop in the subsampling phase-locked loop increases the locking time,a subsampling phase-locked loop architecture based on the dead zone automatic controller is proposed.The quadrature subsampling phase detector is used to identify the phase error and realize the fast switching between loops.Based on this architecture,a millimeter wave wideband fastlocking subsampling phase-locked loop is developed in 40 nm CMOS technology.The output frequency is from 21.8 to 41.6 GHz.The integrated jitter is 62.7 fs,while the locking time is less than 1.5 μs.4.Low power consumption millimeter-wave wideband fractional-N subsampling PLL.In order to solve the problem of high power consumption in the frequency division link of wideband millimeter wave PLL,the frequency locking loop architecture without frequency divider is proposed to avoid the problem caused by millimeter-wave divider.The frequency locking technology based on unequal reference clock delay realizes correct identification and locking of output frequency.Based on 40 nm CMOS technology,the fractional-N PLL is realized.The output frequency range is from 21.8 to41.6 GHz.The integrated jitter is 133.3 fs,while the power consumption of the frequency locking loop is only 0.68 m W.5.Ultra-wideband low jitter low spur phase-locked loop.In order to solve the problem of large jitter and reference spur variations of PLL in a wide output frequency range,an architecture based on constant control voltage compensator with digital programmable control is proposed.Then,a PLL is developed in 40 nm CMOS technology.The output frequency range is from 0.2 to 39.2 GHz.The integrated jitter is66.2 fs,while the reference spur is-71.3 d Bc.